IPR-NIOS Altera, IPR-NIOS Datasheet - Page 141

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 5: Nios II Core Implementation Details
Nios II/f Core
December 2010 Altera Corporation
f
f
1
1
The size of the tag field depends on the size of the cache memory and the physical
address size. The size of the line field depends only on the size of the cache memory.
The size of the offset field depends on the line size. Line sizes of 4, 16, and 32 bytes
have offset widths of 2, 4, and 5 bits respectively. The maximum data byte address size
is 31 bits in systems without an MMU present. In systems with an MMU, the
maximum data byte address size is 32 bits and the tag field always includes all the bits
of the PFN.
The data cache is optional. If the data cache is excluded from the core, the data master
port can also be excluded.
The Nios II instruction set provides several different instructions to clear the data
cache. There are two important questions to answer when determining the instruction
to use. Do you need to consider the tag field when looking for a cache match? Do you
need to write dirty cache lines back to memory before clearing?
most appropriate instruction to use for each case.
Table 5–8. Data Cache Clearing Instructions
The 4-byte line data cache implementation substitutes the flushd instruction for the
flushda instruction and triggers an unimplemented instruction exception for the
initda instruction. The 16-byte and 32-byte line data cache implementations fully
support the flushda and initda instructions.
For more information regarding the Nios II instruction set, refer to the
Reference
The Nios II/f core implements all the data cache bypass methods.
For information regarding the data cache bypass methods, refer to the
Architecture
Mixing cached and uncached accesses to the same cache line can result in invalid data
reads. For example, the following sequence of events causes cache incoherency.
1. The Nios II core writes data to cache, creating a dirty data cache line.
2. The Nios II core reads data from the same address, but bypasses the cache.
Avoid mixing cached and uncached accesses to the same cache line, regardless
whether you are reading from or writing to the cache line. If it is necessary to mix
cached and uncached data accesses, flush the corresponding line of the data cache
after completing the cached accesses and before performing the uncached accesses.
Bursting
When the data cache is enabled, you can enable bursting on the data master port.
Consult the documentation for memory devices connected to the data master port to
determine whether bursting can improve performance.
Write Dirty Lines
Do Not Write Dirty Lines
chapter of the Nios II Processor Reference Handbook.
chapter of the Nios II Processor Reference Handbook
Ignore Tag Field
flushd
initd
Nios II Processor Reference Handbook
Consider Tag Field
Table 5–9
flushda
initda
Processor
Instruction Set
shows the
5–9