IPR-NIOS Altera, IPR-NIOS Datasheet - Page 19

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 1: Introduction
OpenCore Plus Evaluation
OpenCore Plus Evaluation
December 2010 Altera Corporation
Automated System Generation
f
f
For details on the Altera-provided cores, refer to the
Guide.
Custom Peripherals
You can also create custom peripherals and integrate them in Nios II processor
systems. For performance-critical systems that spend most CPU cycles executing a
specific section of code, it is a common technique to create a custom peripheral that
implements the same function in hardware. This approach offers a double
performance benefit: the hardware implementation is faster than software; and the
processor is free to perform other functions in parallel while the custom peripheral
operates on data.
For details on creating custom peripherals, refer to the
chapter in volume 4 of the Quartus II Handbook.
Custom Instructions
Like custom peripherals, custom instructions allow you to increase system
performance by augmenting the processor with custom hardware. The custom logic is
integrated into the Nios II processor’s arithmetic logic unit (ALU). Similar to native
Nios II instructions, custom instruction logic can take values from up to two source
registers and optionally write back a result to a destination register.
Because the processor is implemented on reprogrammable Altera FPGAs, software
and hardware engineers can work together to iteratively optimize the hardware and
test the results of software running on hardware.
From the software perspective, custom instructions appear as machine-generated
assembly macros or C functions, so programmers do not need to understand
assembly language to use custom instructions.
Altera’s SOPC Builder design tool fully automates the process of configuring
processor features and generating a hardware design that you program in an FPGA.
The SOPC Builder graphical user interface (GUI) enables you to configure Nios II
processor systems with any number of peripherals and memory interfaces. You can
create entire processor systems without performing any schematic or HDL design
entry. SOPC Builder can also import HDL design files, providing an easy mechanism
to integrate custom logic in a Nios II processor system.
After system generation, you can download the design onto a board, and debug
software executing on the board. To the software developer, the processor architecture
of the design is set. Software development proceeds in the same manner as for
traditional, nonconfigurable processors.
You can evaluate the Nios II processor without a license. With Altera's free OpenCore
Plus evaluation feature, you can perform the following actions:
■
Simulate the behavior of a Nios II processor within your system
Embedded Peripherals IP User
SOPC Builder Components
Nios II Processor Reference Handbook
1–5