IPR-NIOS Altera, IPR-NIOS Datasheet - Page 87

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Exception Processing
December 2010 Altera Corporation
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Misaligned Data Address
The Nios II processor can check for misaligned data addresses of load and store
instructions and generate an exception when a misaligned data address is
encountered. When your system contains an MMU or MPU, misaligned data address
checking is always on. When no MMU or MPU is present, you have the option to have
the processor check for misaligned data addresses.
To see how to control this option, refer to the
Builder
A data address is considered misaligned if the byte address is not a multiple of the
width of the load or store instruction data width (four bytes for word, two bytes for
half-word). Byte load and store instructions are always aligned so never take a
misaligned address exception.
Misaligned Destination Address
The Nios II processor can check for misaligned destination addresses of the callr,
jmp, ret, eret, bret, and all branch instructions and generate an exception when a
misaligned destination address is encountered. When your system contains an MMU
or MPU, misaligned destination address checking is always on. When no MMU or
MPU is present, you have the option to have the processor check for misaligned
destination addresses.
To see how to control this option, refer to the
Builder
A destination address is considered misaligned if the target byte address of the
instruction is not a multiple of four.
Division Error
The Nios II processor can check for division errors and generate an exception when a
division error is encountered.
To see how to control this option, refer to the
Builder
The division error exception detects divide instructions that produce a quotient that
can't be represented. The two cases are divide by zero and a signed division that
divides the largest negative number -2147483648 (0x80000000) by -1 (0xffffffff).
Division error detection is only available if divide instructions are supported by
hardware.
chapter of the Nios II Processor Reference Handbook.
chapter of the Nios II Processor Reference Handbook.
chapter of the Nios II Processor Reference Handbook.
Instantiating the Nios II Processor in SOPC
Instantiating the Nios II Processor in SOPC
Instantiating the Nios II Processor in SOPC
Nios II Processor Reference Handbook
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