IPR-NIOS Altera, IPR-NIOS Datasheet - Page 100

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–54
Nios II Processor Reference Handbook
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Refer to the
Handbook for details of which processor cores implement bit-31 cache bypass. Refer to
Instruction Set Reference
the cache bypass instructions.
Code written for a processor core with cache memory behaves correctly on a
processor core without cache memory. The reverse is not true. If it is necessary for a
program to work properly on multiple Nios II processor core implementations, the
program must behave as if the instruction and data caches exist. In systems without
cache memory, the cache management instructions perform no operation, and their
effects are benign.
For a complete discussion of cache management, refer to the
Memory
Some consideration is necessary to ensure cache coherency after processor reset. Refer
to
For details on the cache architecture and the memory hierarchy refer to the
Architecture
Virtual Address Aliasing
A virtual address alias occurs when two virtual addresses map to the same physical
address. When an MMU and caches are present and the caches are larger than a page
(4 KB), the operating system must prevent illegal virtual address aliases. Because the
caches are virtually-indexed and physically-tagged, a portion of the virtual address is
used to select the cache line. If the cache is 4 KB or less in size, the portion of the
virtual address used to select the cache line fits with bits 11:0 of the virtual address
which have the same value as bits 11:0 of the physical address (they are untranslated
bits of the page offset). However, if the cache is larger than 4 KB, bits beyond the page
offset (bits 12 and up) are used to select the cache line and these bits are allowed to be
different than the corresponding physical address.
For example, in a 64-KB direct-mapped cache with a 16-byte line, bits 15:4 are used to
select the line. Assume that virtual address 0x1000 is mapped to physical address
0xF000 and virtual address 0x2000 is also mapped to physical address 0xF000. This is
an illegal virtual address alias because accesses to virtual address 0x1000 use line 0x1
and accesses to virtual address 0x2000 use line 0x2 even though they map to the same
physical address. This results in two copies of the same physical address in the cache.
With an n-byte direct-mapped cache, there could be n/4096 copies of the same
physical address in the cache if illegal virtual address aliases are not prevented. The
bits of the virtual address that are used to select the line and are translated bits (bits 12
“Reset Exceptions” on page 3–33
When no MMU is present, bit 31 of the address is reserved for bit-31 cache bypass.
With bit-31 cache bypass, the address space of processor cores is 2 GB, and the
high bit of the address controls the caching of data memory accesses.
When the MMU is present, cacheability is controlled by the MMU, and bit 31
functions as a normal address bit. For details, refer to
Memory Partitions” on page
Cache bypass instructions, such as ldwio and stwio.
chapter of the Nios II Software Developer’s Handbook.
chapter of the Nios II Processor Reference Handbook.
Nios II Core Implementation Details
chapter of the Nios II Processor Reference Handbook for details of
3–4, and
for more information.
“TLB Organization” on page
chapter of the Nios II Processor Reference
“Address Space and
December 2010 Altera Corporation
Cache and Tightly Coupled
Chapter 3: Programming Model
Memory and Peripheral Access
3–6.
Processor