IPR-NIOS Altera, IPR-NIOS Datasheet - Page 57

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Registers
Table 3–5. The Nios II General-purpose Registers (Part 2 of 2)
December 2010 Altera Corporation
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
Notes to
(1) r25 is used exclusively by the JTAG debug module. It is used as the breakpoint temporary (bt) register in the normal register set. In shadow
(2) r30 is used as the breakpoint return address (ba) in the normal register set, and as the shadow register set status (sstatus) in each shadow
Register
register sets, r25 is reserved.
register set. For details about sstatus, refer to
Table
Control Registers
3–5:
f
1
Name
For more information, refer to the
Processor Reference Handbook.
Control registers report the status and change the behavior of the processor. Control
registers are accessed differently than the general-purpose registers. The special
instructions rdctl and wrctl provide the only means to read and write to the control
registers and are only available in supervisor mode.
When writing to control registers, all undefined bits must be written as zero.
The Nios II architecture supports up to 32 control registers.
the defined control registers. All nonreserved control registers have names recognized
by the assembler.
Table 3–6. Control Register Names and Bits (Part 1 of 2)
0
1
2
3
4
5
6
7
Register
Register arguments
Register arguments
Register arguments
Register arguments
Caller-saved register
Caller-saved register
Caller-saved register
Caller-saved register
Caller-saved register
Caller-saved register
Caller-saved register
Caller-saved register
status
estatus
bstatus
ienable
ipending
cpuid
Reserved
exception
Function
Name
“The sstatus Register” on page
Refer to
Refer to
Refer to
Internal interrupt-enable bits
Pending internal interrupt bits
Unique processor identifier
Reserved
Refer to
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
Application Binary Interface
Register
Table 3–7 on page 3–12
Table 3–9 on page 3–14
Table 3–10 on page 3–15
Table 3–11 on page 3–16
3–27.
et
bt
gp
sp
fp
ea
ba
ra
Name
Register Contents
(3)
(3)
Callee-saved register
Callee-saved register
Callee-saved register
Callee-saved register
Exception temporary
Breakpoint temporary
Global pointer
Stack pointer
Frame pointer
Exception return address
Breakpoint return address
Return address
Nios II Processor Reference Handbook
Table 3–6
chapter of the Nios II
Function
shows details of
(1)
(2)
3–11