IPR-NIOS Altera, IPR-NIOS Datasheet - Page 80

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–34
Nios II Processor Reference Handbook
Break Exceptions
1
1
1. Sets status.RSIE to 1, and clears all other fields of the status register.
2. Invalidates the instruction cache line associated with the reset vector.
3. Begins executing the reset handler, located at the reset vector.
All noninterrupt exception handlers must run in the normal register set.
Clearing the status.PIE field disables maskable interrupts. If the MMU or MPU is
present, clearing the status.U field forces the processor into supervisor mode.
Nonmaskable interrupts (NMIs) are not affected by status.PIE, and can be taken
while processing a reset exception.
Invalidating the reset cache line guarantees that instruction fetches for reset code
comes from uncached memory.
Aside from the instruction cache line associated with the reset vector, the contents of
the cache memories are indeterminate after reset. To ensure cache coherency after
reset, the reset handler located at the reset vector must immediately initialize the
instruction cache. Next, either the reset handler or a subsequent routine should
proceed to initialize the data cache.
The reset state is undefined for all other system components, including but not
limited to:
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A break is a transfer of control away from a program’s normal flow of execution for
the purpose of debugging. Software debugging tools can take control of the Nios II
processor via the JTAG debug module.
Break processing is the means by which software debugging tools implement debug
and diagnostic features, such as breakpoints and watchpoints. Break processing is a
type of exception processing, but the break mechanism is independent from general
exception processing. A break can occur during exception processing, enabling debug
tools to debug exception handlers.
General-purpose registers, except for zero (r0) in the normal register set, which is
permanently zero.
Control registers, except for status. status.RSIE is reset to 1, and the remaining
fields are reset to 0.
Instruction and data memory.
Cache memory, except for the instruction cache line associated with the reset
vector.
Peripherals. Refer to the appropriate peripheral data sheet or specification for reset
conditions.
Custom instruction logic. Refer to the
conditions.
Nios II C-to-hardware (C2H) acceleration compiler logic.
Nios II Custom Instruction User Guide
December 2010 Altera Corporation
Chapter 3: Programming Model
Exception Processing
for reset