IPR-NIOS Altera, IPR-NIOS Datasheet - Page 116

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

4–8
Nios II Processor Reference Handbook
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1
Enable Bursts—The Nios II processor can fill its data cache lines using burst
transfers. Usually you enable bursts on the processor's data bus when processor
data is stored in DRAM, and disable bursts when processor data is stored in
SRAM.
Bursting to DRAM typically improves memory bandwidth but might consume
additional FPGA resources. Be aware that when bursts are enabled, accesses to
slaves might go through additional hardware (called “burst adapters”) which
might decrease f
Bursting is only enabled for data line sizes greater than 4 bytes. The burst length is
4 for a 16 byte line size and 8 for a 32 byte line size. Data cache bursts are always
aligned on the cache line boundary. For example, with a 32-byte Nios II data cache
line, a cache miss to the address 8 results in a burst with the following address
sequence: 0, 4, 8, 12, 16, 20, 24 and 28.
Include tightly coupled data master port(s)—When on, the Nios II processor
includes tightly-coupled memory ports. You can specify one to four ports with the
Number of ports setting. Tightly-coupled memory ports appear on the connection
panel of the Nios II processor in the SOPC Builder System Contents tab. You must
connect each port to exactly one memory component in the system.
Although the Nios II processor can operate entirely out of tightly-coupled
memory without the need for Avalon-MM instruction or data masters,
software debug is not possible when either the Avalon-MM instruction or
data master is omitted.
MAX
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Chapter 4: Instantiating the Nios II Processor in SOPC Builder
December 2010 Altera Corporation
Caches and Memory Interfaces Page