IPR-NIOS Altera, IPR-NIOS Datasheet - Page 247

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 8: Instruction Set Reference
Instruction Set Reference
ldbu / ldbuio
December 2010 Altera Corporation
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
31
30
30
29
29
A
A
28
28
27
27
26
26
25
25
24
24
B
B
rB ← 0x000000 : Mem8[rA + σ (IMM16)]
ldbu rB, byte_offset(rA)
ldbuio rB, byte_offset(rA)
ldbu r6, 100(r5)
Computes the effective byte address specified by the sum of rA and the instruction's signed
16-bit immediate value. Loads register rB with the desired memory byte, zero extending the
8-bit value to 32 bits.
In processors with a data cache, this instruction may retrieve the desired data from the cache
instead of from memory. Use the ldbuio instruction for peripheral I/O. In processors with a
data cache, ldbuio bypasses the cache and is guaranteed to generate an Avalon-MM data
transfer. In processors without a data cache, ldbuio acts like ldbu.
For more information on data cache, refer to the
the Nios II Software Developer’s Handbook.
■
■
■
■
■
■
I
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
23
23
Supervisor-only data address
Misaligned data address
TLB permission violation (read)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
22
22
21
21
20
20
Instruction format for ldbuio
19
19
Instruction format for ldbu
18
18
load unsigned byte from memory or I/O peripheral
17
17
16
16
15
15
IMM16
IMM16
14
14
13
13
12
12
Cache and Tightly Coupled Memory
11
11
10
10
9
9
8
8
Nios II Processor Reference Handbook
7
7
6
6
5
5
4
4
0x03
0x23
3
3
chapter of
2
2
1
1
8–61
0
0