IPR-NIOS Altera, IPR-NIOS Datasheet - Page 63

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Registers
Table 3–15. tlbacc Control Register Fields
Table 3–16. tlbacc Control Register Field Descriptions
December 2010 Altera Corporation
31
IG
C
R
W
X
G
PFN
30
Field
29
IG
28
IG is ignored by hardware and available to hold operating system
specific information. Read as zero but can be written as nonzero.
C is the data cacheable flag. When C = 0, data accesses are
uncacheable. When C = 1, data accesses are cacheable.
R is the readable flag. When R = 0, load instructions are not allowed
to access memory. When R = 1, load instructions are allowed to
access memory.
W is the writable flag. When W = 0, store instructions are not allowed
to access memory. When W = 1, store instructions are allowed to
access memory.
X is the executable flag. When X = 0, instructions are not allowed to
execute. When X = 1, instructions are allowed to execute.
G is the global flag. When G = 0, tlbmisc.PID is included in the
TLB lookup. When G = 1, tlbmisc.PID is ignored and only the
virtual page number is used in the TLB lookup.
PFN is the physical frame number field. All unused upper bits must
be zero.
27
26
The tlbacc Register
The tlbacc register is used to access TLB entries and is only available in systems with
an MMU. The tlbacc register holds values that software will write into a TLB entry or
has previously read from a TLB entry. The tlbacc register provides access to only a
portion of a complete TLB entry. pteaddr.VPN and tlbmisc.PID hold the remaining
TLB entry fields.
Table 3–15
Table 3–16
Issuing a wrctl instruction to the tlbacc register writes the tlbacc register with the
specified value. If tlbmisc.WE = 1, the wrctl instruction also initiates a TLB write
operation, which writes a TLB entry. The TLB entry written is specified by the line
portion of pteaddr.VPN and the tlbmisc.WAY field. The value written is specified by
the value written into tlbacc along with the values of pteaddr.VPN and tlbmisc.PID.
A TLB write operation also increments tlbmisc.WAY, allowing software to quickly
modify TLB entries.
Issuing a rdctl instruction to the tlbacc register returns the value of the tlbacc
register. The tlbacc register is written by hardware when software triggers a TLB
read operation (that is, when wrctl sets tlbmisc.RD to one).
25
24
C R W X G
23
22
shows the layout of the tlbacc register.
gives details of the fields defined in the tlbacc register.
21
20
Description
19
18
17
16
15
14
13
12
11
10
PFN
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
9
Access
8
Nios II Processor Reference Handbook
7
6
Reset
5
0
0
0
0
0
0
0
4
3
Available
Only with
Only with
Only with
Only with
Only with
Only with
Only with
MMU
MMU
MMU
MMU
MMU
MMU
MMU
2
1
3–17
0