IPR-NIOS Altera, IPR-NIOS Datasheet - Page 208

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

8–22
br
Nios II Processor Reference Handbook
Operation:
Assembler Syntax:
Example:
Description:
Exceptions:
Instruction Type:
Instruction Fields:
31
30
29
0
28
27
26
25
24
0
PC ← PC + 4 + σ (IMM16)
br label
br top_of_loop
Transfers program control to the instruction at label. In the instruction encoding, the offset
given by IMM16 is treated as a signed number of bytes relative to the instruction immediately
following br. The two least-significant bits of IMM16 are always zero, because instruction
addresses must be word-aligned.
Misaligned destination address
I
IMM16 = 16-bit signed immediate value
23
22
21
20
19
18
17
16
15
IMM16
14
13
12
11
10
9
8
Chapter 8: Instruction Set Reference
December 2010 Altera Corporation
unconditional branch
7
6
5
Instruction Set Reference
4
0x06
3
2
1
0