IPR-NIOS Altera, IPR-NIOS Datasheet - Page 113

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Instantiating the Nios II Processor in SOPC Builder
Caches and Memory Interfaces Page
Caches and Memory Interfaces Page
December 2010 Altera Corporation
Memory Protection Unit Settings
Instruction Master Settings
f
f
1
1
1
The Nios II MMU is optional and mutually exclusive from the Nios II MPU. Nios II
systems can include either an MMU or MPU, but cannot include both an MMU and
MPU in the same design.
For details on the Nios II MMU, refer to the
Processor Reference Handbook.
To function correctly with the MMU, the base physical address of all exception vectors
(reset, general exception, break, and fast TLB miss) must point to low physical
memory so that hardware can correctly map their virtual addresses into the kernel
partition. This restriction is enforced by the Nios II Processor parameter editor.
The Nios II/f core offers a memory protection unit (MPU) to support operating
systems and runtime environments that desire memory protection without the
overhead of virtual memory management. Turning on Include MPU includes the
Nios II MPU in your Nios II hardware system.
The Nios II MPU is optional and mutually exclusive from the Nios II MMU. Nios II
systems can include either an MPU or MMU, but cannot include both an MPU and
MMU in the same design.
For details on the Nios II MPU, refer to the
Processor Reference Handbook.
The Caches and Memory Interfaces page allows you to configure the cache and
tightly-coupled memory usage for the instruction and data master ports.
shows an example of the Caches and Memory Interfaces page.
The following sections describe the configuration settings available.
The Instruction Master settings provide the following options for the Nios II/f and
Nios II/s cores:
■
■
Instruction Cache—Specifies the size of the instruction cache. Valid sizes are from
512 bytes to 64 KBytes, or None.
Choosing None disables the instruction cache, which also removes the
Avalon-MM instruction master port from the Nios II processor. In this case, you
must include a tightly-coupled instruction memory.
Enable Bursts—The Nios II processor can fill its instruction cache lines using burst
transfers. Usually you enable bursts on the processor's instruction master when
instructions are stored in DRAM, and disable bursts when instructions are stored
in SRAM.
Bursting to DRAM typically improves memory bandwidth, but might consume
additional FPGA resources. Be aware that when bursts are enabled, accesses to
Programming Model
Programming Model
Nios II Processor Reference Handbook
chapter of the Nios II
chapter of the Nios II
Figure 4–2
4–5