IPR-NIOS Altera, IPR-NIOS Datasheet - Page 158

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

6–2
Table 6–1. Nios II Processor Revision History (Part 2 of 2)
Architecture Revisions
Table 6–2. Nios II Architecture Revisions (Part 1 of 2)
Nios II Processor Reference Handbook
8.0
7.2
7.1
7.0
6.1
6.0
5.1 SP1
5.1
5.0
1.1
1.01
1.0
10.1
10.0
9.1
Version
Version
December 2010
July 2010
November 2009
Release Date
May 2008
October 2007
May 2007
March 2007
November 2006
May 2006
January 2006
October 2005
May 2005
December 2004
September 2004
May2004
Architecture revisions augment the fundamental capabilities of the Nios II
architecture, and affect all Nios II cores. A change in the architecture mandates a
revision to all Nios II cores to accommodate the new architectural enhancement. For
example, when Altera adds a new instruction to the instruction set, Altera
consequently must update all Nios II cores to recognize the new instruction.
lists revisions to the Nios II architecture.
Release Date
No changes.
No changes.
■
■
Added optional external interrupt controller interface.
Added optional shadow register sets.
■
■
■
■
Added the jmpi instruction.
No changes.
No changes.
No changes.
The name Nios II Development Kit describing the software development tools
changed to Nios II Embedded Design Suite.
Bug fix for Nios II/f core.
No changes.
■
■
■
■
■
■
■
Initial release of the Nios II processor.
Added an optional memory management unit (MMU).
Added an optional memory protection unit (MPU).
Added advanced exception checking.
Added the initda instruction.
Changed version nomenclature. Altera now aligns the Nios II processor
version with Altera's Quartus
Memory structure enhancements:
(1) Added tightly-coupled memory.
(2) Made data cache line size configurable.
(3) Made cache optional in Nios II/f and Nios II/s cores.
Support for HardCopy
Minor enhancements to the architecture: Added cpuid control register,
and updated the break instruction.
Increased user control of multiply and shift hardware in the arithmetic
logic unit (ALU) for Nios II/s and Nios II/f cores.
Minor bug fixes.
Minor bug fixes.
®
devices.
®
Notes
II software version.
Notes
Chapter 6: Nios II Processor Revision History
December 2010 Altera Corporation
Architecture Revisions
Table 6–2