IPR-NIOS Altera, IPR-NIOS Datasheet - Page 30

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–8
Reset and Debug Signals
Table 2–4. Nios II Processor Debug and Reset Signals
Exception and Interrupt Controllers
Nios II Processor Reference Handbook
Signal Name
reset
cpu_resetrequest
debugreq
Exception Controller
f
The Nios II processor core supports several reset and signals, shown in
For more information on adding reset signals to the Nios II processor, refer to
“Advanced Features Page” in the
chapter of the Nios II Processor Reference Handbook. For more information on the break
vector and adding debug signals to the Nios II processor, refer to “JTAG Debug
Module Page” in the
Nios II Processor Reference Handbook.
The Nios II processor includes hardware for handling exceptions, including hardware
interrupts. It also includes an optional external interrupt controller (EIC) interface.
The EIC interface enables you to speed up interrupt handling in a complex system by
adding a custom interrupt controller.
The Nios II architecture provides a simple, nonvectored exception controller to handle
all exception types. Each exception, including internal hardware interrupts, causes the
processor to transfer execution to an exception address. An exception handler at this
address determines the cause of the exception and dispatches an appropriate
exception routine.
Exception addresses are specified in SOPC Builder at system generation time.
Type
Reset
Reset
Debug
Purpose
This is a global hardware reset signal that forces the processor core to reset
immediately.
This is an optional, local reset signal that causes the processor to reset without
affecting other components in the Nios II system. The processor finishes executing any
instructions in the pipeline, and then enters the reset state. This process can take
several clock cycles, so be sure to continue asserting the cpu_resetrequest signal
until the processor core asserts a
The processor core asserts a
complete and then periodically if cpu_resetrequest remains asserted. The processor
remains in the reset state for as long as cpu_resetrequest is asserted. While the
processor is in the reset state, it periodically reads from the reset address. It discards
the result of the read, and remains in the reset state.
The processor does not respond to cpu_resetrequest when the processor is under
the control of the JTAG debug module, that is, when the processor is paused. The
processor responds to the cpu_resetrequest signal if the signal is asserted when
the JTAG debug module relinquishes control, both momentarily during each single step
as well as when you resume execution.
This is an optional signal that temporarily suspends the processor for debugging
purposes. When you assert the signal, the processor pauses in the same manner as
when a breakpoint is encountered, transfers execution to the routine located at the
break address, and asserts a debugack signal. Asserting the debugreq signal when
the processor is already paused has no effect.
Instantiating the Nios II Processor in SOPC Builder
Instantiating the Nios II Processor in SOPC Builder
cpu_resettaken signal for 1 cycle when the reset is
cpu_resettaken signal.
December 2010 Altera Corporation
Chapter 2: Processor Architecture
Reset and Debug Signals
chapter of the
Table
2–4.