IPR-NIOS Altera, IPR-NIOS Datasheet - Page 60

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–14
Table 3–8. status Control Register Field Descriptions (Part 3 of 3)
Table 3–9. estatus Control Register Fields
Nios II Processor Reference Handbook
PIE
Notes to
(1) The CRS field is read-only. For information about manually changing register sets, refer to
(2) The state where both EH and U are one is illegal and causes undefined results.
(3) When this field is unimplemented, the field value always reads as 0, and the processor behaves accordingly.
(4) When this field is unimplemented, the field value always reads as 1, and the processor behaves accordingly.
31
Bit
30
page
29
Table
3–36.
PIE is the processor interrupt-enable bit. When PIE = 0, internal and
maskable external interrupts and noninterrupt exceptions are ignored.
When PIE = 1, internal and maskable external interrupts can be taken,
depending on the status of the interrupt controller. Noninterrupt exceptions
are unaffected by PIE.
Reserved
28
3–8:
f
1
27
26
The estatus Register
The estatus register holds a saved copy of the status register during nonbreak
exception processing.
All fields in the estatus register have read/write access. All fields reset to 0.
Table 3–8
When the Nios II processor takes an interrupt, if status.eh is zero (that is, the MMU
is in nonexception mode), the processor copies the contents of the status register to
estatus.
If shadow register sets are implemented, and the interrupt requests a shadow register
set, the Nios II processor copies status to sstatus, not to estatus.
For details about the sstatus register, refer to
The exception handler can examine estatus to determine the pre-exception status of
the processor. When returning from an exception, the eret instruction restores the
pre-exception value of status. The instruction restores the pre-exception value by
copying either estatus or sstatus back to status, depending on the value of
status.CRS.
Refer to
25
24
23
“Exception Processing” on page 3–30
describes the details of the fields defined in the estatus register.
22
21
Description
20
19
PRS
Table 3–9
18
17
16
shows the layout of the estatus register.
15
14
13
CRS
12
“The sstatus Register” on page
for more information.
11
“External Interrupt Controller Interface” on
10
9
Read/Write
Access
8
December 2010 Altera Corporation
7
IL
Chapter 3: Programming Model
6
5
Reset
0
4
3
Available
Always
2
3–27.
Registers
1
0