IPR-NIOS Altera, IPR-NIOS Datasheet - Page 163

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 6: Nios II Processor Revision History
JTAG Debug Module Revisions
JTAG Debug Module Revisions
Table 6–6. JTAG Debug Module Revisions
December 2010 Altera Corporation
10.1
10.0
9.1
9.0
8.1
8.0
7.2
7.1
7.0
6.1
6.0
5.1
5.0
1.1
1.01
1.0
Version
December 2010
July 2010
November 2009
March 2009
November 2008
May 2008
October 2007
May 2007
March 2007
November 2006
May 2006
October 2005
May 2005
December 2004
September 2004
May 2004
Release Date
JTAG debug module revisions augment the debug capabilities of the Nios II
processor, or fix bugs isolated within the JTAG debug module logic.
Table 6–6
lists revisions to the JTAG debug module.
No changes.
No changes.
No changes.
No changes.
No changes.
No changes.
No changes.
No changes.
No changes.
No changes.
No changes.
No changes.
Support for HardCopy devices (previous versions of the JTAG debug module did not
support HardCopy devices).
Bug fix:
When using the Nios II/s and Nios II/f cores, hardware breakpoints may have falsely
triggered when placed on the instruction sequentially following a jmp, trap, or any
branch instruction.
■
■
Initial release of the JTAG debug module.
Feature enhancements:
(1) Added the ability to trigger based on the instruction address. Uses include
triggering trace control (trace on/off), sequential triggers, and trigger in/out
signal generation.
(2) Enhanced trace collection such that collection can be stopped when the trace
buffer is full without halting the Nios II processor.
(3) Armed triggers – Enhanced trigger logic to support two levels of triggers, or
"armed triggers"; enabling the use of "Event A then event B" trigger definitions.
Bug fixes:
(1) On the Nios II/s core, trace data sometimes recorded incorrect addresses
during interrupt processing.
(2) Under certain circumstances, captured trace data appeared to start earlier or
later than the desired trigger location.
(3) During debugging, the processor would hang if a hardware breakpoint and an
interrupt occurred simultaneously.
Notes
Nios II Processor Reference Handbook
6–7