IPR-NIOS Altera, IPR-NIOS Datasheet - Page 16

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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Getting Started with the Nios II Processor
Nios II Processor Reference Handbook
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A Nios II processor system is equivalent to a microcontroller or “computer on a chip”
that includes a processor and a combination of peripherals and memory on a single
chip. A Nios II processor system consists of a Nios II processor core, a set of on-chip
peripherals, on-chip memory, and interfaces to off-chip memory, all implemented on a
single Altera device. Like a microcontroller family, all Nios II processor systems use a
consistent instruction set and programming model.
Getting started with the Nios II processor is similar to any other microcontroller
family. The easiest way to start designing effectively is to purchase a development kit
from Altera that includes a ready-made evaluation board and the Nios II Embedded
Design Suite (EDS) containing all the software development tools necessary to write
Nios II software.
The Nios II EDS includes the following two closely-related software development tool
flows:
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Both tools flows are based on the GNU C/C++ compiler. The Nios II SBT for Eclipse
provides a familiar and established environment for software development. Using the
Nios II SBT for Eclipse, you can immediately begin developing and simulating Nios II
software applications.
The Nios II SBT also provides a command line interface.
Dedicated instructions for computing 64-bit and 128-bit products of multiplication
Floating-point instructions for single-precision floating-point operations
Single-instruction barrel shifter
Access to a variety of on-chip peripherals, and interfaces to off-chip memories and
peripherals
Hardware-assisted debug module enabling processor start, stop, step, and trace
under control of the Nios II software development tools
Optional memory management unit (MMU) to support operating systems that
require MMUs
Optional memory protection unit (MPU)
Software development environment based on the GNU C/C++ tool chain and the
Nios II Software Build Tools (SBT) for Eclipse
Integration with Altera's SignalTap
real-time analysis of instructions and data along with other signals in the FPGA
design
Instruction set architecture (ISA) compatible across all Nios II processor systems
Performance up to 250 DMIPS
The Nios II SBT
The Nios II SBT for Eclipse
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II Embedded Logic Analyzer, enabling
Getting Started with the Nios II Processor
December 2010 Altera Corporation
Chapter 1: Introduction