IPR-NIOS Altera, IPR-NIOS Datasheet - Page 53

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Memory Management Unit
December 2010 Altera Corporation
TLB Lookups
1
The tag portion of a TLB entry contains information used when matching a virtual
address to a TLB entry.
Table 3–3. TLB Tag Portion Contents
The TLB data portion determines how to translate a matching virtual address to a
physical address.
Table 3–4. TLB Data Portion Contents
Because there is no “valid bit” in the TLB entry, the operating system software
invalidates the TLB by writing unique VPN values from the I/O partition of virtual
addresses into each TLB entry.
A TLB lookup attempts to convert a virtual address (VADDR) to a physical address
(PADDR).
The TLB lookup algorithm for instruction fetches is shown in
Example 3–1. TLB Lookup Algorithm for Instruction Fetches
if (VPN match && (G == 1 || PID match))
else
VPN
PID
G
PFN
C
R
W
X
Field Name
Field Name
if (X == 1)
else
if (EH bit of status register == 1)
else
PADDR = concat(PFN, VADDR[11:0])
take TLB permission violation exception
take double TLB miss exception
take fast TLB miss exception
PFN is the physical frame number field. This field specifies the upper bits of the
physical address. The size of this field depends on the range of physical addresses
present in the system. The maximum size is 20 bits.
C is the cacheable flag. Determines the default data cacheability of a page. Can be
overridden for data accesses using I/O load and store family of Nios II instructions.
R is the readable flag. Allows load instructions to read a page.
W is the writable flag. Allows store instructions to write a page.
X is the executable flag. Allows instruction fetches from a page.
VPN is the virtual page number field. This field is compared with the top 20 bits of
the virtual address.
PID is the process identifier field. This field is compared with the value of the
current process identifier stored in the tlbmisc control register, effectively
extending the virtual address. The field size is configurable at system generation
time, and can be between 8 and 14 bits.
G is the global flag. When G = 1, the PID is ignored in the TLB lookup.
Table 3–4
Table 3–3
describes the data portion of a TLB entry.
describes the tag portion of a TLB entry.
Description
Description
Nios II Processor Reference Handbook
Example
3–1.
3–7