IPR-NIOS Altera, IPR-NIOS Datasheet - Page 241

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 8: Instruction Set Reference
Instruction Set Reference
initd
December 2010 Altera Corporation
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
30
29
A
28
27
26
25
24
0
Initializes the data cache line associated with address rA + σ (IMM16).
initd IMM16(rA)
initd 0(r6)
If the Nios II processor implements a direct mapped data cache, initd clears the data cache
line without checking for (or writing) a dirty data cache line that is mapped to the specified
address back to memory. Unlike initda, initd clears the cache line regardless of whether the
addressed data is currently cached. This process comprises the following steps:
■
■
■
■
■
If the Nios II processor core does not have a data cache, the initd instruction performs no
operation.
Use initd after processor reset and before accessing data memory to initialize the processor’s
data cache. Use initd with caution because it does not write back dirty data. By contrast, refer
to
page
options. Altera recommends using initd only when the processor comes out of reset.
For more information on data cache, refer to the
the Nios II Software Developer’s Handbook.
Supervisor-only instruction
I
A = Register index of operand rA
IMM16 = 16-bit signed immediate value
“flushd flush data cache line” on page
Compute the effective address specified by the sum of rA and the signed 16-bit immediate
value.
Identify the data cache line associated with the computed effective address. Each data cache
effective address comprises a tag field and a line field. When identifying the line, initd
ignores the tag field and only uses the line field to select the data cache line to clear.
Skip comparing the cache line tag with the effective address to determine if the addressed
data is currently cached. Because initd ignores the cache line tag, initd flushes the cache
line regardless of whether the specified data location is currently cached.
Skip checking if the data cache line is dirty. Because initd skips the dirty cache line check,
data that has been modified by the processor, but not yet written to memory is lost.
Clear the valid bit for the line.
23
8–52, and
22
21
20
“initda initialize data cache address” on page 8–56
19
18
17
16
15
IMM16
14
8–51,
13
12
“flushda flush data cache address” on
Cache and Tightly Coupled Memory
11
10
9
initialize data cache line
8
Nios II Processor Reference Handbook
7
for other cache-clearing
6
5
4
0x33
3
chapter of
2
1
8–55
0