IPR-NIOS Altera, IPR-NIOS Datasheet - Page 62

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–16
Table 3–11. exception Control Register Field Descriptions
Table 3–12. exception Control Register Fields
Table 3–13. pteaddr Control Register Fields
Table 3–14. pteaddr Control Register Field Descriptions
Nios II Processor Reference Handbook
CAUSE
31
31
PTBASE
VPN
Field
30
30
Field
29
29
28
28
PTBASE
CAUSE is written by the Nios II processor when certain exceptions
occur. CAUSE contains a code for the highest-priority exception
occurring at the time. The Cause column in
page 3–32
CAUSE is not written on a break or an external interrupt.
PTBASE is the base virtual address of the page table.
VPN is the virtual page number. VPN can be set by both hardware
and software.
27
27
26
26
To see how to control the extra exception information option, refer to the
the Nios II Processor in SOPC Builder
Table 3–11
Table 3–12
The pteaddr Register
The pteaddr register contains the virtual address of the operating system’s page table
and is only available in systems with an MMU. The pteaddr register layout
accelerates fast TLB miss exception handling.
pteaddr register.
Table 3–14
Software writes to the PTBASE field when switching processes. Hardware never writes
to the PTBASE field.
Software writes to the VPN field when writing a TLB entry. Hardware writes to the VPN
field on a fast TLB miss exception, a TLB permission violation exception, or on a TLB
read operation. The VPN field is not written on any exceptions taken when an
exception is already active, that is, when status.EH is already one.
25
25
shows the CAUSE field value for each exception.
24
24
23
23
22
22
shows the layout of the exception register.
gives details of the fields defined in the exception register.
gives details of the fields defined in the pteaddr register.
21
21
Description
20
20
Description
Reserved
19
19
18
18
17
17
16
16
Table 3–33 on
15
15
chapter of the Nios II Processor Reference Handbook.
14
14
13
13
12
12
VPN
Table 3–13
11
11
10
10
Read/Write
Read/Write
9
9
Access
Access
Read
shows the layout of the
8
8
December 2010 Altera Corporation
7
7
Chapter 3: Programming Model
6
6
Reset
Reset
5
5
0
0
0
CAUSE
4
4
Instantiating
information
3
3
Available
exception
Available
Only with
Only with
Only with
MMU
MMU
extra
2
2
Registers
Rsvd
Rsvd
1
1
0
0