IPR-NIOS Altera, IPR-NIOS Datasheet - Page 79
IPR-NIOS
Manufacturer Part Number
IPR-NIOS
Description
IP NIOS II MEGACORE RENEW
Manufacturer
Altera
Type
MegaCorer
Datasheet
1.IP-NIOS.pdf
(294 pages)
Specifications of IPR-NIOS
License
Renewal License
Lead Free Status / RoHS Status
Not applicable / Not applicable
- Current page: 79 of 294
- Download datasheet (3Mb)
Chapter 3: Programming Model
Exception Processing
Table 3–33. Nios II Exceptions (In Decreasing Priority Order) (Part 2 of 2)
December 2010 Altera Corporation
Supervisor-only Data
Address
Misaligned Data Address
Misaligned Destination
Address
Division Error
Fast TLB Miss (data)
Double TLB Miss (data)
TLB Permission Violation
(read)
TLB Permission Violation
(write)
MPU Region Violation
(data)
Notes to
(1) It is possible for any instruction fetch to cause this exception.
(2) Refer to
(3) For a description of the requested handler address, refer to
Table
Exception
Exception Latency
Reset Exceptions
Table 3–5 on page 3–10
3–33:
Exception latency specifies how quickly the system can respond to an exception.
Exception latency depends on the type of exception, the software and hardware
configuration, and the processor state.
Interrupt Latency
The interrupt controller can mask individual interrupts. Each interrupt can have a
different maximum masked time. The worst-case interrupt latency for interrupt i is
determined by that interrupt’s maximum masked time, or by the maximum disabled
time, whichever is greater.
When a processor reset signal is asserted, the Nios II processor performs the following
steps:
Instruction-related
Instruction-related
Instruction-related
Instruction-related
Instruction-related
Instruction-related
Instruction-related
Instruction-related
Instruction-related
for descriptions of the ea and ba registers.
Type
MMU
Illegal memory
access
detection on,
MMU, or MPU
Illegal memory
access
detection on,
MMU, or MPU
Division error
detection on
MMU
MMU
MMU
MMU
MPU
“Requested Handler Address” on page
Available
11
6
7
8
12
12
14
15
17
Cause
badaddr (data
address)
badaddr (data
address)
badaddr
(destination
address)
ea–4
pteaddr.VPN,
badaddr (data
address)
pteaddr.VPN,
badaddr (data
address)
pteaddr.VPN,
badaddr (data
address)
pteaddr.VPN,
badaddr (data
address)
badaddr (data
address)
Address
3–36.
(2)
Nios II Processor Reference Handbook
General exception
General exception
General exception
General exception
Fast TLB Miss
exception
General exception
General exception
General exception
General exception
Vector
3–33
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