IPR-NIOS Altera, IPR-NIOS Datasheet - Page 101

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Instruction Set Categories
Instruction Set Categories
Table 3–38. Wide Data Transfer Instructions
Table 3–39. Narrow Data Transfer Instructions
December 2010 Altera Corporation
ldw
stw
ldwio
stwio
ldb
ldbu
stb
ldh
ldhu
sth
ldbio
ldbuio
stbio
ldhio
ldhuio
sthio
Instruction
Instruction
Data Transfer Instructions
The ldw and stw instructions load and store 32-bit data words from/to memory. The effective address is the
sum of a register's contents and a signed immediate value contained in the instruction. Memory transfers can
be cached or buffered to improve program performance. This caching and buffering might cause memory
cycles to occur out of order, and caching might suppress some cycles entirely.
Data transfers for I/O peripherals should use ldwio and stwio.
ldwio and stwio instructions load and store 32-bit data words from/to peripherals without caching and
buffering. Access cycles for ldwio and stwio instructions are guaranteed to occur in instruction order and
are never suppressed.
ldb, ldbu, ldh and ldhu load a byte or half-word from memory to a register. ldb and ldh sign-extend the
value to 32 bits, and ldbu and ldhu zero-extend the value to 32 bits.
stb and sth store byte and half-word values, respectively.
Memory accesses can be cached or buffered to improve performance. To transfer data to I/O peripherals,
use the “io” versions of the instructions, described below.
These operations load/store byte and half-word data from/to peripherals without caching or buffering.
and up) are known as the color of the address. An operating system avoids illegal
virtual address aliases by ensuring that if multiple virtual addresses map the same
physical address, the virtual addresses have the same color. Note though, the color of
the virtual addresses does not need to be the same as the color as the physical address
because the cache tag contains all the bits of the PFN.
This section introduces the Nios II instructions categorized by type of operation
performed.
The Nios II architecture is a load-store architecture. Load and store instructions
handle all data movement between registers, memory, and peripherals. Memories and
peripherals share a common address space. Some Nios II processor cores use memory
caching and/or write buffering to improve memory bandwidth. The architecture
provides instructions for both cached and uncached accesses.
Table 3–38
The data transfer instructions in
describes the wide (32-bit) load and store instructions.
Table 3–39
Description
Description
support byte and half-word transfers.
Nios II Processor Reference Handbook
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