IPR-NIOS Altera, IPR-NIOS Datasheet - Page 50

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–4
Table 3–1. MMU Virtual Address Fields
Table 3–2. Virtual Memory Partitions (Part 1 of 2)
Nios II Processor Reference Handbook
31
I/O
Kernel
Kernel MMU
30
Partition
(1)
(1)
29
Address Space and Memory Partitions
28
(1)
1
27
26
0xE0000000–0xFFFFFFFF
0xC0000000–0xDFFFFFFF
0x80000000–0xBFFFFFFF
Table 3–1
virtual page number (VPN) and a 12 bit page offset.
As input, the TLB takes a VPN plus a process identifier (to guarantee uniqueness). As
output, the TLB provides the corresponding physical frame number (PFN).
Distinct processes can use the same virtual address space. The process identifier,
concatenated with the virtual address, distinguishes identical virtual addresses in
separate processes. To determine the physical address, the Nios II MMU translates a
VPN to a PFN and then concatenates the PFN with the page offset. The bits in the
page offset are not translated.
Memory Protection
The Nios II MMU maintains read, write, and execute permissions for each page. The
TLB provides the permission information when translating a VPN. The operating
system can control whether or not each process is allowed to read data from, write
data to, or execute instructions on each particular page. The MMU also controls
whether accesses to each data page are cacheable or uncacheable by default.
Whenever an instruction attempts to access a page that either has no TLB mapping, or
lacks the appropriate permissions, the MMU generates an exception. The Nios II
processor’s precise exceptions enable the system software to update the TLB, and then
re-execute the instruction if desired.
The MMU provides a 4-gigabyte (GB) virtual address space, and is capable of
addressing up to 4 GB of physical memory.
The amount of actual physical memory, determined by the configuration of your
hardware system, might be less than the available 4 GB of physical address space.
Virtual Memory Address Space
The 4-GB virtual memory space is divided into partitions. The upper 2 GB of memory
is reserved for the operating system and the lower 2 GB is reserved for user processes.
Table 3–2
25
Virtual Address Range
24
Virtual Page Number
23
shows how the Nios II MMU divides up the virtual address. There is a 20 bit
names and describes the partitions.
22
21
20
19
18
17
Operating
Operating
Operating
16
Used By
system
system
system
15
14
13
Memory Access
Bypasses TLB
Bypasses TLB
12
Uses TLB
11
10
9
8
User Mode
December 2010 Altera Corporation
7
Page Offset
Access
Chapter 3: Programming Model
No
No
No
6
Memory Management Unit
5
4
Default Data
Cacheability
Set by TLB
3
Disabled
Enabled
2
1
0