IPR-NIOS Altera, IPR-NIOS Datasheet - Page 146

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–14
Table 5–11. eic_port_data Signal
Nios II/s Core
Nios II Processor Reference Handbook
44
JTAG Debug Module
f
1
The EIC interface presents the following signals to the Nios II processor through the
eic_port_data signal:
■
■
■
■
Table 5–11
Following Avalon-ST protocol requirements, the EIC interface samples eic_port_data
only when eic_port_valid is asserted (high). When eic_port_valid is not asserted,
the processor latches the previous values of RHA, RRS, RIL and RNMI. To present
new values on eic_port_data, the EIC must transmit a new packet, asserting
eic_port_valid. An EIC can transmit a new packet once per clock cycle.
For an example of an EIC implementation, refer to the Vectored Interrupt Controller
chapter in the
The Nios II/f core supports the JTAG debug module to provide a JTAG interface to
software debugging tools. The Nios II/f core supports an optional enhanced interface
that allows real-time trace data to be routed out of the processor and stored in an
external debug probe.
The Nios II MMU does not support the JTAG debug module trace.
The Nios II/s standard core is designed for small core size. On-chip logic and memory
resources are conserved at the expense of execution performance. The Nios II/s core
uses approximately 20% less logic than the Nios II/f core, but execution performance
also drops by roughly 40%. Altera designed the Nios II/s core with the following
design goals in mind:
■
■
Requested handler address (RHA)—The 32-bit address of the interrupt handler
associated with the requested interrupt
Requested register set (RRS)—The six-bit number of the register set associated
with the requested interrupt
Requested interrupt level (RIL)—The six-bit interrupt level. If RIL is 0, no
interrupt is requested.
Requested nonmaskable interrupt (RNMI) flag—A one-bit flag indicating whether
the interrupt is to be treated as nonmaskable
Do not cripple performance for the sake of size.
Remove hardware features that have the highest ratio of resource usage to
performance impact.
RHA
...
shows the field positions in eic_port_data.
Embedded Peripherals IP User
13
12
Guide.
RRS
...
Chapter 5: Nios II Core Implementation Details
7
December 2010 Altera Corporation
6
5
RIL
...
Nios II/s Core
0