tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 76

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.5.4
Port 3 (P30-P37)
or output, with the exception that P30 and P31 are output-only. The control register P3CR and function
register P3FC are used to set the port for input or output. A reset sets bits P30, P31 and P37 of the output
latch to 1. Bits P32 to P36 are set to 1 by a reset if RSTPUP is High or cleared to 0 if RSTPUP is Low.
All bits of P3CR (bits 0 and 1 not used) and P3FC (bits 3 and 7 not used) are cleared to 0 by a reset, with
P30 and P31 outputting a High signal and P32 to P36 placed in input mode with pull-up resistors enabled
(if RSTPUP is High) or disabled (if RSTPUP is Low). P37 is placed in input mode with a pull-up resistor
enabled regardless of the value of RSTPUP.
the CPU's control and status signals. The RD strobe is output only when an external address area is being
accessed while the P30 pin is set for RD output (<P30F> = 1). Similarly, the WR strobe is output only
when an external address area is being accessed while the P31 pin is set for WR output (<P31F> = 1).
Port 3 is an 8-bit general-purpose input/output port whose bits can each be set independently for input
In addition to functioning as a general-purpose input/output port, this port can also input and output
P32 and P36 have their pull-up resistors enabled when BUSAK = 0 while <P3xFC> = 1.
Write to P3FC
Function Control
Write to P3
Output Latch
Reset
(bitwise)
S
Read P3
Figure 0.7 Port 3 (P30, P31)
TMP1942CY/CZ-75
RD , WR
A
B
S
Output Buffer
TMP1942CY/CZ
P30 ( RD )
P31 ( WR )