tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 157

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Address bus
Data bus
•
Figure 3.8.13 Diagram of Data Transfer in Single-Address Mode
Dual-address mode
-Read operation, in which the DMAC outputs the address of the source device, reads data from
-Write operation, in which the DMAC outputs the address of the destination device and writes
-Memory-to-memory
-Memory-to-I/O device
-I/O device-to-memory
16 bits or 8 bits) specified in the TrSiz field of the CCRn register. This amount of data is
transferred each time a transfer request is recognized.
device into the DHR register, then the data is written from the DHR register to the destination
device.
When external memory is accessed, if the transfer unit is 32 bits and the bus width set by the
CS/wait controller is 16 bits, then two 16-bit accesses will occur. Similarly, if the transfer unit
is 32 bits and the bus width set by the CS/wait controller is 8 bits, then four 8-bit accesses will
occur.
In dual-address mode, a data transfer is executed using two bus operations:
the source device and stores the data in its internal register DHR
the stored data from DHR to the destination device
In dual-address mode, three types of transfers can be performed:
The units of data transfer performed by the DMAC are equal to the amount of data (32 bits,
In dual-address mode, an amount of data equal to the transfer unit is read from the source
Memory accesses occur at intervals equal to the unit of data transfer which has been set.
DMAC
TMP1942CY/CZ-156
Address
DACK
Source device (I/O)
Destination device
(memory)
TMP1942CY/CZ
Data