tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 351

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Note: Even when the chip is reset by the watchdog timer, the PLLOFF pin is sampled. Thus, the
PLLOFF pin must be held at a constant logic level, either High or Low.
WDT Counter
WDT Interrupt
WDT Clear (Software)
WDT Counter
WDT Interrupt
Internal Reset
binary counter outputs are available: 2
selected using WDMOD<WDTP1:WDTP0>, so that when the selected counter output overflows, a
watchdog timer interrupt will be generated, as shown in Figure 3.19.2.
reset for a period of 22 to 29 states as shown in Figure 3.19.3. When the chip is reset in this way, the
watchdog timer is clocked by a clock of fsys, instead of by the afore-mentioned input clock fsys/2. The
fsys clock is derived by dividing the high-speed oscillator's clock fC by a clock gear of 8.
The watchdog timer consists of a 22-stage binary counter clocked by the system clock fsys/2. Four
Also, it is possible to reset the chip itself when the counter output overflows. In this case, the chip is
n
n
22 to 29 states (8.8~11.6 μs @ f
Figure 3.19.2 Normal Mode
Figure 3.19.3 Reset Mode
TMP1942CY/CZ-350
Overflow
15
, 2
Overflow
17
, 2
19
and 2
C
21
= 40 MHz, f
. Any one of these counter outputs can be
Write Clear Code
sys
TMP1942CY/CZ
= 5 MHz, f
sys/2
= 2.5 MHz)
0