tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 248
tmp19a43fzxbg
Manufacturer Part Number
tmp19a43fzxbg
Description
32bit Tx System Risc
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP19A43FZXBG.pdf
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Note:FERR reading occurs during the interruption handling must be executed before a receive buffer reading.
(11) Error flags
(12) Direction of data transfer
Polling for reading FERR is prohibited.
See the example in 3.11.4 (3) Mode 2 (8-bit UART Mode) for the details.
setting SCnMOD2<DRCHG>. Do not change the direction of transfer while data is being
transferred.
1.
2.
3.
Three error flags are available for the purpose of increasing the reliability of the received data.
In I/O interface mode, the direction of transfer can be toggled between MSB first and LSB first by
Overrun error <OERR>
frame have been received before data stored in the receive buffer is read out completely. An
overrun error causes the OERR flag to be set. Reading the flag clears it to 0. If SCLK output is
selected in I/O interface mode, however, this flag is undefined because no overrun error will
occur.
Parity error/underrun error <PERR>
the parity calculated from the received data differs from the received parity bit. Reading the
PERR flag clears it to 0.
is set to 1, an underrun error occurs in the following case: In SCLK input mode, it occurs if data
stored in the transmit shift register has been transmitted but no data is set in the transmit
double-buffer before the next transfer clock is input. In SCLK output mode, this flag is
undefined because no underrun error will occur. The PERR flag is not set when transmit buffer
2 is disabled. Reading the flag clears it to 0.
Framing error <FERR>
clears it to 0. A framing error occurs if the stop bit in the received data is detected as being 0
when sampled around the center.
UART
I/O interface
(SCLK input)
I/O interface
(SCLK output)
Operating Mode
In both UART and I/O interface modes, an overrun error occurs when all bits of the next
In UART mode, the PERR flag is set to 1 when a parity error occurs. A parity error occurs if
In I/O interface mode, the PERR bit indicates an underrun error. When SC0MOD2<WBUF>
In UART mode, the FERR flag is set to 1 when a framing error occurs. Reading the flag
TMP1942CY/CZ-247
OERR
PERR
FERR
OERR
PERR
FERR
OERR
PERR
FERR
Error Flag
Overrun error flag
Parity error flag
Framing error flag
Overrun error flag
Underrun error flag (WBUF = 1)
Fixed to 0 (WBUF = 0)
Fixed to 0
Undefined
Undefined
Fixed to 0
TMP1942CY/CZ
Description
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