tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 44

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

*
The INTRTC interrupt must have its active state set to a rising edge in the CG even when it is not
used for standby termination.
Note: Each stage must be completed in the following sequence: set the active level, clear the
INTRTC*
INT0 ∼ A/
IMCGA0<EMCG01:00> = “10”
EICRCG<ICRCG2:0> = “000”
IMCGA0<INT0EN> = “1”
IMC0L<EIM11:10> = “01”
INTCLR<EICLR5:0> = “000001”
IMC0L<IL12:10> = “101”
Status<IEc> = “1”, <CMask> = “xxx”
Interrupt?
Set INTC
interrupt request, and then enable the interrupt.
Figure 3.44.2 Flow for Setting External Interrupts
(Example of setting INT0 for standby termination)
Set INTC (High level)
INTB ∼ E
KWUP0 ∼ D
Set KWUPSTn or
INTnST
TMP1942CY/CZ-43
End
: Select falling edge for INT0
: Clear interrupt request for INT0C G block
: Enable request input for INT0
: Select High level for INT0
: Clear interrupt request for INT0
: Set interrupt level to 5
Set INTC (High level)
Set CG
INT0 ∼ 4
INTRTC
NO
Set KWUPSTn or INTnST
Set INTC (High level)
Standby termination
Set CG (High level)
TMP1942CY/CZ
Interrupt?
Start
INTB ∼ E
KWUP0 ∼ D
YES
INTC block
TX19 processor core