tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 153

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Transfer Request
(5) Channel operation
(6) Summary of transfer mode combinations
bit (Str) in the channel control register (CCRn) to 1, so that the device enters ready state.
the bus and performs a data transfer. When there are no more transfer requests, the DMAC
finishes control of the bus, thereby entering ready state. When transfer for a channel is
completed, the channel is placed in idle state. Transfers may be terminated either normally or
abnormally (for example, when an error occurs during transfer). An interrupt signal can be
generated on completion of transfer.
settings.
External
Internal
Stop
The DMAC has four channels (channels 0 to 3). Each channel is activated by setting the start
When a transfer request occurs while a channel is in ready state, the DMAC gains control of
Figure 3.8.11 is a state transition diagram for channel operations.
The DMAC can perform data transfers as follows according to the combination of mode
Figure 3.8.11 State Transitions for Channel Operations
Transfer
completed
Edge/Level
Start
Low-level
Bus control not
owned by DMAC
⎯
TMP1942CY/CZ-152
Address Mode
Transfer
Ready
Dual
Dual
Bus control owned by DMAC
Bus control owned by DMAC
Bus control not
owned by DMAC
Memory-to-memory
Memory-to-memory
Memory-to-I/O
I/O-to-memory
Transfer Devices
TMP1942CY/CZ