tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 245

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(6) Receive buffer
(7) Transmit counter
TXDCLK
SIOCLK
one bit at a time in receive buffer 1 (a shift register). When all bits of data have been received, the
data is transferred to another receive buffer, receive buffer 2 (SC0BUF), at which point an INTRX0
interrupt is generated. Also, the receive buffer full flag (SC0MOD2<RBFLL>) is set to 1
simultaneously, indicating that receive buffer 2 contains valid data.
cleared to 0. Next received data can be stored in receive buffer 1 even before the CPU reads the data
out from receive buffer 2 (SC0BUF).
or disabled by setting SC0MOD2<WBUF> accordingly. Disabling receive buffer 2 allows the
device to handshake with the remote device it is communicating with, so that it stops CLK output
every time it has sent a single frame. In that case, the CPU reads data from receive buffer 1. This read
causes CLK output to restart. When receive buffer 2 is enabled in I/O interface mode, operation is as
follows: The first received data is transferred from receive buffer 1 to receive buffer 2. CLK output
stops when the next data has been received and both receive buffers 1 and 2 contain valid data. Once
the CPU has read data from receive buffer 2, the data in receive buffer 1 is transferred to receive
buffer 2, at which point an INTRX0 interrupt is generated and CLK output is restarted. Therefore, no
overrun error occurs in SCLK output I/O interface mode, regardless of the WBUG setting.
continuous transfer. However, if the CPU has not read the data out from receive buffer 2 (SC0BUF)
by the time all the bits of the next data item have been received into receive buffer 1, an overrun error
will occur. If an overrun error occurs, the contents of receive buffer 1 will be lost; the contents of
receive buffer 2 and SC0CR<RB8> will be retained.
significant bit of 9-bit UART data.
SC0MOD0<WU> to 1. In this case, an INTRX0 interrupt is only generated if SC0CR<RB8> = 1.
receive counter, this counter is incremented every time a SIOCLK pulse is detected and generates a
transmit clock (TXDCLK) pulse every 16 SIOCLK pulses.
Note: In this mode the SC0CR OEER flag has no meaning, resulting in undefined
The receive buffer has double-buffer structure to prevent overrun errors. Received data is stored
The CPU reads data from receive buffer 2 (SC0BUF). This read causes the RBFLL flag to be
When SCLK output is selected in I/O interface mode, receive buffer 2 (SCOBUF) can be enabled
In other operating modes, receive buffer 2 is always enabled to improve performance for
SC0CR<RB8> stores either the parity bit which is added to 8-bit UART data or the most
In 9-bit UART mode, slave controller wake-up operation can be enabled by setting
The transmit counter is a 4-bit binary counter used in asynchronous (UART) mode. Like the
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operation. Be sure to read SC0CR to initialize this flag before changing the mode
from SCLK output mode.
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Figure 3.11.3 Generating a Transmit Clock
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