tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 354

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.19.3
Functional Description
generates an interrupt (INTWDT). The binary counter for the watchdog timer must be cleared to zero by
software before an INTWDT interrupt can occur. If runaway occurs in the CPU due to noise or other
causes, and prevents the CPU from executing the instruction to clear the binary counter, the binary
counter will overflow and generate an INTWDT interrupt. This interrupt notifies the CPU that it has
gone out of control, so that the CPU can restore itself to a normal condition by executing a program to
correct the runaway condition. Also, output from the watchdog timer can be transmitted to the reset pin
or other pins of peripheral devices to address the CPU runway condition.
= Low), it will continue to count. In IDLE mode, the WDMOD<I2WDT> setting determines whether the
watchdog timer is on or off. Before placing the device into IDLE mode, set WDMOD<I2WDT> as
required.
Examples:
After the detection time which has been set in WDMOD<WDT1:WDT0>, the watchdog timer
The watchdog timer will start operating as soon as the device has completed its reset sequence.
In SLEEP and STOP modes, the watchdog timer is reset and remains idle. If the bus is free ( BUSAK
1) Clearing the binary counter
2) Setting the watchdog timer detection time to 2
3) Disabling the watchdog timer
WDCR
WDMOD
WDMOD
WDCR
← 0 1 0 0 1 1 1 0
← 1 0 1 − − − − −
← 0 − − − − − − −
← 1 0 1 1 0 0 0 1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
TMP1942CY/CZ-353
Write clear code (4EH).
Clear WDTE to 0.
Write disable code (B1H).
18
/fsys
TMP1942CY/CZ