tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 120

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.6.2
Note: fsys expresses one period of share of system clock.
A [23 : 16]
AD [15 : 0]
ALE
A [23 : 16]
AD [15 : 0]
ALE
WR
RD
External bus operation
to be A23-A16 and the address/data bus is chosen to be AD15-AD0.
(1) Basic bus operation
This section explains various bus timings. In the following timing diagrams, the address bus is chosen
inserted, as will be explained later. The basic clock for external bus cycles is the same as the internal
system clock.
access, the address bus does not change, as shown in the diagram, nor does ALE output a latch pulse.
The address/data bus is placed in high-impedance state, and neither
signals are asserted.
External bus cycles in the TMP1942 essentially consist of three clock cycles. A wait state can be
Figure 3.6.1 shows a read bus timing. Figure 3.6.2 shows a write bus timing. During internal
Figure 3.6.1 Read Operation Timing Diagram
Figure 3.6.2 Write Operation Timing Diagram
tsys
ADR
ADR
External access
TMP1942CY/CZ-119
External area
tsys
DATA
DATA
Holds upper address
Does not output ALE
Does not output
Does not output ALE
Does not output
Holds upper address
Enter Hi-Z state
Enter Hi-Z state
Internal access
Internal area
WR
RD
TMP1942CY/CZ
RD
and
WR
nor other control