tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 45

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.4.3
Resolving interrupt priority
(1) Seven interrupt priority levels
(2) Notification of the interrupt level
(3) Interrupt vector (notification of interrupt source)
set to one of seven levels.
includes a 3-bit level-setting field (ILx). The greater the value (interrupt level) set in
IMC<ILx2:ILx0>, the higher the interrupt priority. If the value set for an interrupt source in this field
is 000 (i.e., the interrupt level is set to 0), no interrupt is generated for that interrupt source.
interrupt. The TX19 processor core recognizes the interrupt level by reading the IL field in the Cause
register. If multiple interrupts (with different priority levels) occur simultaneously, the TX19
processor core is notified of the interrupt with the highest priority.
the vector register (IVR). The TX19 processor core reads the vector register to determine the
interrupt source. If multiple interrupts (with the same priority level) occur simultaneously, the TX19
processor core is notified of the vector for the interrupt source with the smallest request number.
When there are no interrupt sources for which an interrupt has occurred, the IVR[9:4] field is 0.
processor core. The processor core sets the Status<CMask> bit with the interrupt level which it
reads.
The TMP1942 has seven interrupt priority levels; thus for each interrupt source the priority can be
The interrupt mode control register (IMCx) is used for setting interrupt levels. This register
When an interrupt occurs, the INTC notifies the TX19 processor core of the priority level of the
When an interrupt occurs, the INTC also sets the vector for the source of the generated interrupt in
When it is time for the TX19 processor core to read the vector register value, the INTC notifies the
TMP1942CY/CZ-44
TMP1942CY/CZ