tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 295

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.12.6
Data Transfer Procedure in I
(1) Initializing the device
(2) Generating a start condition and slave address
Settings in the main routine
Example of INTS2 interrupt routine processing
clear bits 7-5 and 3 of SBI0CR1 to 0.
format.
SBI0CR2<PIN> to 1, SBI0CR2<SBIM1:SBIM0> to 10 and clear bits 1 and 0 of SBI0CR2 to 00.
1)
SBI0BR1 ← 1 0 0 0 0 0 0 0
SBI0CR1 ← 0 0 0 X 0 X X X
I2C0AR
SBI0CR2 ← 0 0 0 1 1 0 0 0
Reg.
Reg.
if Reg. ≠ 0x00
Then
SBI0CR1 ← X X X 1 0 X X X
SBI0DR1 ← X X X X X X X X
SBI0CR2 ← 1 1 1 1 1 0 0 0
INTCLR
Processing
End of interrupt processing
(Note) X: Don’t care
First, set SBI0BR1<P4EN> and SBI0CR1<ACK, SCK2:SCK0>. Set SBI0BR1<P4EN> to 1 and
Next, set the slave address in I2C0AR<SA6:SA0> and set I2C0AR<ALS> to 0 for addressing
Then, to initialize the device to slave receiver mode, set SBI0CR2<MST, TRX, BB> to 000,
In master mode
master mode:
acknowledgment mode by setting SBI0CR1<ACK> to 1. Also, write the slave address and
direction bit to SBI0DBR.
condition on the bus. Then output nine clock pulses on the SCL pin. For the first eight clock
pulses, output the slave address and direction bit which have been set in SBI0DBR. Release the
SDA line on the ninth clock pulse to receive an acknowledge signal from the slave device.
SBI0CR2<PIN> to 0. In master mode, the SCL line is held Low while PIN = 0. In addition,
only when an acknowledge signal is returned from the slave device, the generation of an INTS2
interrupt request causes SBI0CR2<TRX> to change state according to the transmitted direction
bit.
Follow the procedure described below to generate a start condition and slave address in
First, check that the bus is free (SBI0SR<BB> = 0). Next, place the serial bus into
While SBI0SR<BB> = 0, set SBI0CR2<MST, TRX, BB, PIN> to 1111 to generate a start
An INTS2 interrupt request is generated at the falling edge of the ninth clock pulse, resetting
← X X X X X X X X
← SBI0SR
← Reg. e 0x20
← 0X34
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
TMP1942CY/CZ-294
2
C Bus Mode
Operate internal baud rate generator.
Set ACK and SCL clocks.
Set slave address and address recognition mode.
Select slave receiver mode.
Check that bus is free.
Select acknowledgement mode.
Set slave address and direction for target slave.
Generate start condition.
Clear interrupt request.
TMP1942CY/CZ