tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 197

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Note: Programming the TB0CLK[1:0] and TB0CLE bits in the TB0MOD register should only be
Note: Programming the TB0RDE bit should only be attempted when the timer is not running.
(2) Up-counter (UC0)
(3) Timer registers (TB0RG0H/L and TB0RG1H/L)
TB0MOD<TB0CLK1:TB0CLK0>.
prescaler output clocks, φT1, φT4 or φT16. The setting of TB0RUN<TB0RUN> either causes the
up-counter UC0 to count, or stops and clears it. If the value in the up-counter UC0 matches the value
in the timer register TB0RG1H/L while clearing is enabled, UC0 is cleared to 0. Clearing of UC0 can
be enabled or disabled by setting TB0MOD<TB0CLE> accordingly.
overflows, it generates an overflow interrupt INTTB01.
counter mode is selected with the setting of TB2RUN<TB2UDCE>, UC0 functions as an
up/down-counter with an initial value of 0x7FFF. When the counter overflows, it is reloaded with an
initial value of 0x0000. When the counter underflows, it is reloaded with an initial value of 0xFFFF.
UC0 only functions as an up-counter in other modes.
one of these timer registers matches the value of up-counter UC0, the comparator’s match detection
signal becomes active.
data transfer instruction, or in two operations (the eight low-order bits first and then the eight
high-order bits) using a 1-byte data transfer instruction.
setting of TB0RUN<TB0RDE> enables or disables the register’s double-buffer facility. The
double-buffer is disabled when <TB0RDE> = 0 and enabled when <TB0RDE> = 1. When the
double-buffer is enabled, data transfer from register buffer 0 to the timer register TB0RG0 is initiated
by a match of UC0 and TB0RG1.
must be written to the timer registers before the 16-bit timers can be used. A reset initializes
TB0RUN<TB0RDE> to 0, disabling the double-buffer. To use the double-buffer, write data to the
timer registers and set <TB0RDE> to 1, then write the following data in the register buffer.
allocated to them. When <TB0RDE> = 0, the same value is written to TB0RG0 and its register
buffer; when <TB0RDE> = 1, the value is only written to the register buffer. Therefore, the register
buffer must be disabled before the initial value is written to the timer register.
attempted when the timer is not running.
UC0 is a 16-bit binary counter which counts up synchronously with the input clock selected by
The input clock for UC0 is either the external clock entered via the TB0IN0 pin or one of the three
If clearing is disabled, the counter functions as a free-running counter. In addition, when UC0
TMRB2 and TMRB3 support the 2-phase pulse input counter feature. When 2-phase pulse
Each channel incorporates two 16-bit registers used to set a counter value. When the value set in
Timer registers TB0RG0H/L and TB0RG1H/L can be written in a single operation using a 2-byte
The timer register TB0RG0 has a double-buffer structure, being paired with register buffer 0. The
When reset, the contents of the timer registers TB0RG0 and TB0RG1 are undefined; hence, data
TB0RG0 and its register buffer both have the same addresses, 0xFFFF_F188 and 0xFFFF_F189,
TMP1942CY/CZ-196
TX1942CY/CZ