tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 343

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

INTEST
(0xFFFF_F383) Read/Write
INTFLG
(0xFFFF_F384) Read/Write
Note: Setting procedures
Bit symbol
After Reset
Function
Bit symbol
After Reset
Function
A) When setting INT inputs first after powering up the device
B) When modifying the active condition for an INT input during operation
C) When enabling an INT input during operation
1) Set the active conditions using the INTnST corresponding to the interrupt inputs to be used.
2) Clear the interrupt request by reading INTFLG.
3) Set the INTnST<INTnEN> corresponding to the interrupt inputs to be used to 1.
4) Set the CG and INTC (refer to Section 3.4, “Interrupts” for details).
1) Disable INTBCD interrupts in the INTC (IMC1<26:24> = 000).
2) Modify the active condition for the INT input using the corresponding INTnST.
3) Clear the interrupt request by reading INTFLG.
4) Enable INTBCD interrupts in the INTC (set IMC1<26:24> to an appropriate level).
1) Disable INTBCD interrupts in the INTC (IMC1<26:24> = 000).
2) Set the active condition using the INTnST corresponding to the interrupt input to be used.
3) Clear the interrupt request by reading INTFLG.
4) Set the INTnST<INTnEN> corresponding to the interrupt input to be used to 1.
5) Enable INTBCD interrupts in the INTC (set IMC1<26:24> to an appropriate level).
⎯
⎯
⎯
⎯
⎯
⎯
7
7
⎯
⎯
⎯
⎯
⎯
⎯
6
6
TMP1942CY/CZ-342
Sets INTE active
condition
00: Low level
01: High level
10: Falling edge
11: Rising edge
INTE1
⎯
⎯
⎯
5
5
1
R/W
INTE0
⎯
⎯
⎯
4
4
0
0: Interrupt
1: Interrupt
not
generated
generated
INTES
⎯
⎯
⎯
3
3
0
0: Interrupt
1: Interrupt
INTDS
not
generated
generated
TMP1942CY/CZ
⎯
⎯
⎯
2
2
0
R
0: Interrupt
1: Interrupt
not
generated
generated
INTCS
⎯
⎯
⎯
1
1
0
0: Interrupt
1: Interrupt
INTE
interrupt
input
0: Disable
1: Enable
INTEEN
not
generated
generated
INTBS
R/W
0
0
0
0