tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 139

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

BEXCS
(0xFFFF_E488)
3.7.3
Figure 3.7.7 Example of External Memory Connection (ROM width = 16 bits, RAM width = 16 bits)
Example of Use
In this example a 128-Kbyte ROM is connected with a data width of 16 bits and 256-Kbyte RAM is
connected with a data width of 16 bits.
both cleared to 0, so that the CS signal output is disabled. To output a CS signal from this port, set the
corresponding bits in these registers to 1, first in P4FC and then in P4CR.
Note: “Please set the number of wait as “+1” when you use = long and BUSRQ the ALE width.”
TMP1942
Figure 3.7.7 shows an example of a TMP1942 system configuration with external memory connected.
When the TMP1942 is reset, the port 4 control register (P4CR) and port 4 function register (P4FC) are
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
AD8 - 15
A16 - 17
AD0 - 7
HWR
ALE
CS
AM1
AM0
RD
CS
WR
2
1
Selects chip select
output waveform.
00: ROM/RAM
Other settings are not
allowed.
Figure 3.7.6 Chip select/wait control registers
15
⎯
⎯
⎯
7
0
BEXOM
Latch × 16
W
D Q
LE
14
⎯
⎯
⎯
6
0
TMP1942-138
A1 - 15
A1 - 15
13
⎯
⎯
⎯
⎯
⎯
⎯
5
A16 - 17
A16 - 17
A1 - 15
A16
Selects
data bus
width.
0: 16 bits
1: 8 bits
BEXBUS
12
⎯
⎯
⎯
4
0
A15
A0 - 14
A15 - 16
A0 - 14
A15 - 16
A0 - 14
OE
CE
OE
/ R
CE
OE
/ R
CE
W
W
1
1
ROM (128 Kbits × 16)
Sets the number of wait cycles
0000-0111: 0 cycles to 7 cycles
1111: (1+N) cycles
RAM (128 Kbits × 8)
RAM (128 Kbits × 8)
11
⎯
⎯
⎯
3
0
Lower byte
Upper byte
Other settings are not allowed.
TMP1942CY/CZ
10
W
⎯
⎯
⎯
2
1
D8 - 15
I/01 - 8
I/01 - 8
BEXW
D0 - 7
Sets the number of
dummy cycles to be
inserted.
(Read recovery time)
00: 2 cycles
01: 1 cycle
10: None
11: Setting not
allowed
1
0
9
0
BEXRCV
W
0
1
8
0