tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 274

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Timing at which received
data is written to buffer
SCLK0 output
RXD0
(INTRX0 interrupt request)
Timing at which received
data is written to buffer
SCLK0 output
RXD0
(INTRX0 interrupt request)
RBFULL
Timing at which received
data is written to buffer
SCLK0 output
RXD0
(INTRX0 interrupt request)
RBFULL
Figure 3.11.38 Receive Operation in I/O Interface Mode (SCLK0 Output Mode)
2)
Reception
synchronizing clock is output on the SCLK0 pin and the next data item is shifted into receive
buffer 1 each time the received data is read by the CPU. When 8 bits of data have been received,
an INTRX0 interrupt is generated.
double-buffer is enabled, the received frame is transferred to transmit buffer 2 and then the next
frame is received into receive buffer 1. When data has been transferred from receive buffer 1 to
receive buffer 2, SCnMOD2<RBFLL> is set to 1 and an INTRX0 interrupt occurs.
have been received, an overrun error occurs, setting SCnCR<OERR>. In that case, SCLK0
output is stopped without generating an INTRX0 interrupt. After an overrun error occurs,
reading data from receive buffer 2 causes the data in receive buffer 1 to be transferred to
receive buffer 2, generating an INTRX0 interrupt to restart reception.
If WBUF = 0, that is, the receive double-buffer is disabled in SCLK output mode, the
SCLK output is initiated by setting SC0MOD0<RXE> to 1. If WBUF = 1, that is, the receive
If the CPU/DMAC does not read data from receive buffer 2 before the next eight bits of data
bit7
bit7
When WBUF = 1 (if data is not read from buffer 2)
When WBUF = 1 (if data is read from buffer 2)
bit 0
bit 0
bit 0
TMP1942CY/CZ-273
When WBUF = 0
bit 1
bit 1
bit 1
bit 6
bit 6
bit 6
TMP1942CY/CZ
bit 7
bit 7
bit 7
bit 0
bit 0