tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 188

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

up-counter 0 match
TA01RUN
TA01MOD
TA0REG
TA1FFCR
P7CR
P7FC
TA01RUN
(compare value)
Note: X = Don’t care; “—” = No change
Register buffer
TA0REG and
2
n
-1 overflow
into TA0REG upon the detection of a 2
requirements for small duty cycle waveforms.
E×ample: To output the following PWM waveform on the TA1OUT pin using TMRA0 when
must be satisfied:
TA0REG
If TA0REG has its double-buffer enabled in this mode, the value in the register buffer is shifted
To achieve a PWM cycle of 31.75 μs with φT1 = 0.25 μs (at fc = 32 MHz), the following equation
31.75 μs/0.25 μs = 127 = 2
Therefore, n must be set to 7.
Since the Low-level period is 18 μs and φT1 = 0.25 μs,
18 μs/0.25 μs = 72 = 48H
Therefore, TA0REG must be set to 48H.
MSB
← −
← 1
← 0
← X
← −
← −
← 1
*Clock conditions
7
fc = 32 MHz
6
X
1
1
X
−
−
X
Up-counter = Q
Figure 3.9.23 Register Buffer Operation
18 μs
5
X
1
0
X
−
−
X
31.75 μs
4
X
0
0
X
−
−
X
LSB
3
−
−
1
1
−
−
−
Q
Q
1
2
2
−
−
0
0
−
−
1
n
1
-1
TMP1942CY/CZ-187
1
−
0
0
1
1
1
−
System clock:
High-speed clock gear:
Prescaler clock:
0
0
X
1
0
1
−
−
n
-1 overflow. Using the double-buffer facilitates satisfying the
Shift to TA0REG
Stops TMRA0 and clear it to 0.
Select 8-bit PWM mode (cycle = 2
φT1.
Write 48H.
Clear TA1FF and enable inversion.
Set PA6 to TA1OUT output pin.
Start TMRA0.
Up-counter = Q
High-speed (fc)
× 1 (fc)
fperiph/4 (fperiph = fsys)
Q
Write to TA0REG
(register buffer)
2
2
TMP1942CY/CZ
Q
3
7
-1) and set input clock to