tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 332

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.
3.14 Digital/Analog Converter
3.14 Digital/Analog Converter
3.14.1
3.14.1
3.14.2
3.14.2
This section describes the D/A converter the TMP1942 contains.
This section describes the D/A converter the TMP1942 contains.
CLR Controller
Setting DACCNTn<REFON> to 0 enables reduction of current consumption by decreasing Iref.
Features
Features
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Operation
Operation
the VALID bit to the output register pair DAREGnL/DAREGnH causes the voltage corresponding to the
the VALID bit to the output register pair DAREGnL/DAREGnH causes the voltage corresponding to the
output code to appear on the DAOUTn output pin. The value in the output registers will be reflected in
output code to appear on the DAOUTn output pin. The value in the output registers will be reflected in
DAOUT only if the VALID bit is set. Therefore, when updating the code, set the VALID bit if 10-bit data
DAOUT only if the VALID bit is set. Therefore, when updating the code, set the VALID bit if 10-bit data
has been updated in DAREGnH first and then DAREGnL. Once the VALID bit has been set to 1, the
has been updated in DAREGnH first and then DAREGnL. Once the VALID bit has been set to 1, the
value stored in DAREGnL/H is fetched into the D/A converter as 10-bit data, which will be recognized
value stored in DAREGnL/H is fetched into the D/A converter as 10-bit data, which will be recognized
as code. Setting DACCNTn<OP> to 0 places the DAOUTn output pin into the high-impedance state.
as code. Setting DACCNTn<OP> to 0 places the DAOUTn output pin into the high-impedance state.
Setting DACCNTn<REFON> to 0 enables reduction of current consumption by decreasing Iref.
When the OP and REFON bits of the control register DACCNTn are set to 1s, writing output code and
When the OP and REFON bits of the control register DACCNTn are set to 1s, writing output code and
Three 10-bit D/A converter channels.
Three 10-bit D/A converter channels.
Each channel contains a full-range buffer amplifier.
Each channel contains a full-range buffer amplifier.
Each channel can be placed in standby state using control registers.
Each channel can be placed in standby state using control registers.
DACCNTn
V
Opn
Figure 3.14.1 D/A Converter Block Diagram
Figure 3.14.1 D/A Converter Block Diagram
DAREGnL
REFONn
TMP1942CY/CZ-331
W
DAC
2
System Diagram for DACn
Internal DAREG (10 bits)
DAREFHH
DAREGnH
10
AVSS
8
DAOUTn
TMP1942CY/CZ