tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 402

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8. Notations, Precautions and Restrictions
8.1 Notations and Terms
8.2 Precautions and Restrictions
(1) I/O register fields are often referred to as <register_mnemonic>.<field_name> for the interest of brevity.
(2) fc, fs, fsys, state
(1) Processor Revision Identifier
(2) BW0 to BW1 Pins
(3) Oscillator Warm-Up Counter
(4) Programmable Pull-up Resistors
(5) External Bus Mastership
(6) Watchdog Timer (WDT)
(7) A/D Converter (ADC)
For example, TRUN.T0RUN means the T0RUN bit in the TRUN register.
The fsys cycle is referred to as a state.
In addition, the clock selected by the SYSCR1.FPSEL bit and the prescaler clock source selected by the
SYSCR0.PRCK[1:0] bits are referred to as fperiph and φT0 respectively.
The Process Revision Identifier (PRId) register in the TX19 core of the TMP1942 contains 0x0000_2C91.
The BW0 and BW1 pins must be connected to the DVCC pin to ensure that their signal levels do not
fluctuate during chip operation.
If an external crystal is utilized, an interrupt signal programmed to bring the TMP1942 out of STOP mode
triggers the on-chip warm-up counter. The system clock is not supplied to the on-chip logic until the
warm-up counter expires.
When port pins are configured as input ports, the integrated pull-up resistors can be enabled and disabled
under software control. The pull-up resistors are not programmable when port pins are configured as
output ports.
The relevant port registers are programmed with the data resistor.
The pin states while the bus is granted to an external device are described in Chapter 7, I/O Ports.
Upon reset, the WDT is enabled. If the watchdog timer function is not required, it must be disabled after
reset. When relevant pins are configured as bus arbitration signals, the I/O peripherals including the WDT
can operate during external bus mastership.
The ladder resistor network between the VREFH and VREFL pins can be disconnected under software
control. This helps to reduce power dissipation, for example, in STOP mode.
fosc:
fpll:
fc:
fs:
fgear: Clock selected by the SYSCR1.GEAR[1:0] bits
fsys:
Clock supplied from the X1 and X2 pins
Clock generated by the on-chip PLL
Clock selected by the PLLOFF pin
Clock selected by the SYSCR1.SYSCK bit
Clock supplied from the XT1 and XT2 pins
TMP1942CY/CZ-401
TMP1942CY/CZ