tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 390

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.3.4
6.3.5
6.3.6
115
3
Boundary-scan registe
TMS and TDI sampled on rising edge of TCK
TCK
Instruction register
Bypass register
Test Access Port (TAP)
TAP Controller
Controller Reset
test data and instructions are communicated over these five signal pins, along with control of the test to be
executed.
register, or the Boundary-scan register) from the TDI pin, or it is scanned from one of these three registers
onto the TDO pin.
independent of any chip-specific or system clocks.
the TDO pin changes on the falling edge of the TCK clock signal.
Data scanned in serially
The Test Access Port (TAP) consists of the five signal pins:
As Figure shows, data is serially scanned into one of the three registers (Instruction register, Bypass
The TMS input controls the state transitions of the main TAP controller state machine.
The TCK input is a dedicated test clock that allows serial JTAG data to be shifted synchronously,
Data on the TDI and TMS pins is sampled on the rising edge of the TCK input clock signal. Data on
The processor implements the 16-state TAP controller as defined in the IEEE JTAC specification.
The TAP controller state machine can be put into Reset state the following:
In either case, keeping TMS asserted maintains the Reset state.
•
•
0
assertion of the
keeping the TMS input signal asserted through five consecutive rising edges of TCK input.
0
0
Figure 6.3.4 JTAG Test Access Port
TRST
TMP1942CY/CZ-389
TDI pin
TMS pin
signal (Low) resets the TAP controller.
115
Boundary-scan register
3
Instruction register
Bypass register
TDO sampled on falling edge of TCK
0
Data scanned out serially
TRST
0
0
, TDI, TDO, TMS, and TCK. Serial
TMP1942CY/CZ
TDO pin