tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 70

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Note: The above system diagram does not represent the address/data bus function.
3.5.1
Port 0 (P00-P07)
or output. Use the control register P0CR to set the port for input or output. A reset clears all bits of P0CR
to 0 and puts port 0 in input mode.
address/data bus (AD0-AD7). When external memory is accessed, this port automatically functions as an
address/data bus (AD0-AD7), with all bits of P0CR cleared to 0.
Port 0 is an 8-bit general-purpose input/output port whose bits can each be set independently for input
In addition to functioning as a general-purpose input/output port, this port can also function as an
Direction Control
Write to P0CR
Output Latch
Write to P0
(bitwise)
Reset
Figure 0.1 Port 0 (P00-P07)
TMP1942CY/CZ-69
Read P0
Output Buffer
TMP1942CY/CZ
STOP
DRIVE
Port 0
P00-P07
(AD0-AD7)