tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 297

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Figure 3.12.13 Example in Which SBI0CR1<BC2:BC0> = 000 and SBI0CR1<ACK> = 1 (Transmitter Mode)
SCL pin
SDA pin
<PIN>
INTS2 Interrupt Request
Figure 3.12.14 Example in Which SBI0CR1<BC2:BC0> = 000 and SBI0CR1<ACK> = 1 (Receiver Mode)
SCL
SDA
<PIN>
INTS2 Interrupt Request
Write to SBI0DBR
INTS2 interrupt
if MST = 0
Then go to slave mode processing
if TRX = 0
Then go to receiver mode processing
if LRB = 0
Then go to processing for generating stop condition
SBI0CR1 ← X X X X 0 X X X
SBI0DBR ← X X X X X X X X
End of interrupt processing
Note: X: Don't care
In receiver mode (when SBI0SR<TRX> = 0)
is not 8 bits long, set SBI0CR1<BC2:BC0> and SBI0CR1<ACK> and then read the received
data from SBI0DBR in order to release the SCL line. (The data read out immediately after the
transmission of the slave address is undefined.) When data is read from the data buffer register,
SBI0CR2<PIN> is set to 1. The serial clock for transferring the next word of data is output on
the SCL pin. The SDA pin is pulled Low at the final bit when the acknowledge signal goes
Low.
is pulled Low. Each time received data is read from SBI0DBR, a clock pulse for one-word data
transfer and an acknowledge signal are output.
If the next data item to be transferred is 8 bits long, write the transfer data to SBI0DBR. If it
An INTS2 interrupt request is now generated, SBI0CR2<PIN> is reset to 0 and the SCL pin
D7
Read received data
D7
1
1
D6
D6
2
2
TMP1942CY/CZ-296
D5
D5
3
3
D4
D4
4
4
Set number of bits to be transferred and ACK.
Write transfer data.
D3
D3
5
5
D2
D2
6
6
D1
D1
7
7
TMP1942CY/CZ
D0
D0
8
8
Master output
Slave output
Master output
Slave output
ACK
ACK
9
9
Ack signal
from receiver
Ack signal to
transmitter
Next D7