tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 186

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Note: X = Don’t care; “—” = No change
TA01RUN
TA01MOD
TA0REG
TA1REG
TA1FFCR
P7CR
P7FC
TA01RUN
into TA0REG when TA1REG and UC0 match.
requirements for small duty cycle waveforms.
E×ample: To output a 1/4 duty cycle 50-kHz pulse (fc = 32 MHz)
φT1 = 0.25 μs (at fc = 32 MHz),
TA0REG and up-
TA1REG and up-
If TA0REG has its double-buffer enabled in this mode, the value in the register buffer is shifted
If it is necessary to change the duty cycle, using the double-buffer facilitates satisfying the
Calculate the values to be set in the timer registers as follows:
To obtain a frequency of 50 kHz, generate a waveform with a period t = 1/50 kHz = 20 μs. When
20 μs/0.25 μs = 80
Therefore, TA1REG must be set to 80 (= 50H).
Ne×t, to obtain a 1/4 duty cycle, using the formula t × 1/4 = 20 μs × 1/4 = 5 μs,
5 μs/0.25 μs = 20
Therefore, TA0REG must be set to 20 (= 14H).
(compare value)
counter 0 match
counter 0 match
Register buffer
← 0
← 1
← 0
← 0
← X
←
←
← 1
TA0REG
*Clock conditions
7
−
−
6
X
0
0
1
X
−
−
X
Figure 3.9.20 Register Buffer Operation
5
X
X
0
0
X
−
−
X
20 μs
4
X
X
1
1
X
−
−
X
3
−
X
0
0
0
−
−
−
(Up-counter = Q
2
0
X
1
0
1
−
−
1
TMP1942CY/CZ-185
System clock:
High-speed clock gear:
Prescaler clock:
1
0
0
0
0
1
1
1
1
Q
1
0
0
1
0
0
X
−
−
1
Q
1
2
)
Stop TMRA0 and TMRA1 and clear them to 0.
Select 8-bit PPG mode and set input clock to φT1.
Write 14H.
Write 50H.
Set TA1FF and enable inversion.
If these bits are set to 10, Low-active output waveform will
be obtained.
Set PA6 to TA1OUT output pin.
Start TMRA0 and TMRA1.
(Up-counter = Q
High-speed (fc)
× 1 (fc)
fperiph/4 (fperiph = fsys)
Shift to register buffer
TMP1942CY/CZ
2
Q
)
2
Write to TA0REG
(register buffer)
Q
3