tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 137

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

B01CS
(0xFFFF_E480)
3.7.2
Chip select/wait control registers
(i.e., the CS0-CS3 spaces and any other address space), the corresponding chip select/wait control
register (B01CS-B23CS or BEXCS) can be used to enable/disable the master, select a chip select output
waveform and data bus width, set the number of wait cycles and insert dummy cycles. If two or more
address spaces are specified which overlap one another, the address space with the lowest CS space
number will be selected since it has priority. (The priority order is CS0 > CS1 > CS2 > CS3 > EXCS.)
Note: “Please set the number of wait as “+1” when you use = long and BUSRQ the ALE width.”
The chip select/wait control registers are shown in Figure 3.7.4 to Figure 3.7.6. For each address space
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
B01CS (0xFFFF_E480), B23CS (0xFFFF_E484), BEXCS (0xFFFF_E488)
Selects chip select
output waveform.
00: ROM/RAM
Other settings are not
allowed.
Selects chip select
output waveform.
00: ROM/RAM
Other settings are not
allowed.
Figure 3.7.4 Chip select/wait control registers
15
23
31
⎯
⎯
⎯
⎯
⎯
⎯
7
0
0
B0OM
B1OM
W
W
14
22
30
⎯
⎯
⎯
⎯
⎯
⎯
6
0
0
TMP1942-136
13
21
29
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
5
Selects
data bus
width.
0: 16 bits
1: 8 bits
Selects
data bus
width.
0: 16 bits
1: 8 bits
B0BUS
B1BUS
12
20
28
⎯
⎯
⎯
⎯
⎯
⎯
4
0
0
CS0
enable
0: Disable
1: Enable
CS1
enable
0: Disable
1: Enable
Sets the number of wait cycles
0000: 0 cycles 0001: 1 cycle
0011: 3 cycles 0100: 4 cycles 0101: 5 cycles
0110: 6 cycles 0111: 7 cycles
1111: (1+N) cycles
Sets the number of wait cycles
0000: 0 cycles 0001: 1 cycle
0011: 3 cycles 0100: 4 cycles 0101: 5 cycles
0110: 6 cycles 0111: 7 cycles
1111: (1+N) cycles
B0E
B1E
19
11
27
W
W
3
0
0
0
0
Other settings are not allowed.
Other settings are not allowed.
TMP1942CY/CZ
18
10
26
W
⎯
⎯
⎯
W
⎯
⎯
⎯
2
1
1
B0W
B1W
Sets the number of
dummy cycles to be
inserted.
(Read recovery time)
00: 2 cycles
01: 1 cycle
10: None
11: Setting not allowed
Sets the number of
dummy cycles to be
inserted.
(Read recovery time)
00: 2 cycles
01: 1 cycle
10: None
11: Setting not allowed
17
25
1
0
9
0
0
0
0010: 2 cycles
0010: 2 cycles
B0RCV
B1RCV
W
⎯
8
16
24
0
1
0
1
0