tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 131

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.7
3.7.1
Note: Use physical addresses in the BMAn registers.
sizes, data bus width, wait state insertion, and dummy cycle insertion for back-to-back bus cycles.
chip select signals are generated when the CPU or on-chip DMAC issues an address within the programmed
ranges. The P40-P43 pins must be configured as CS0-CS3 by programming the Port 4 Control (P4CR) register
and the Port 4 Function (P4FC) register.
Address (BMAn) register for each of the four chip select signals, where n is a number from 0 to 3.
consists of a master enable bit, a data bus width bit, a wait state field and a dummy cycle field.
write bus cycles.
(1) Base/Mask Address Registers
The TMP1942 supports direct connections to external devices (I/O devices, ROM and SRAM).
The TMP1942 provides four programmable chip select signals. Programmable features include variable block
Chip select address ranges are defined in terms of a base address and an address mask. There is a Base/Mask
There is also a set of three Chip Select/Wait Control registers, B01CS, B23CS and BEXCS, each of which
External memory devices can also use the
CS
Chip Select/Wait Controller
allows one of the chip select output signals (
within a particular programmed range. The B01CS register defines specific operations for CS0 and CS1, and
the B23CS register defines specific operations for CS2 and CS3 (see Section 3.7.2).
0
Each of the four chip select address ranges is defined in the BMAn register. The basic chip select model
-
CS
Programming Chip Select Ranges
field specifies the starting address for a chip select. Any set bit in the address mask field (MAn) masks the
corresponding base address bit. The address mask field determines the block size of a particular chip
select line. The address is compared on every bus cycle.
/Base address
/Address mask
The organizations of the BMAn registers are shown in Fig.3.7.1 and Fig. 3.7.2. The base address (BAn)
3
The base address (BAn) field specifies the upper 16 bits (A31-A16) of the starting address for a chip
select. The lower 16 bits (A15-A0) are assumed to be zero. Thus, the base address is any multiple of
64 Kbytes starting at 0x0000_0000. Figure 3.7.3 shows the relationships between starting addresses
and the BMAn values.
The address mask (MAn) field defines whether any particular bits of the address should be
compared or masked. Any set bit masks the corresponding base address bit. The address compare
logic uses only the address bits that are not masked (i.e., mask bit cleared to 0) to detect an address
match.
Address bits that can be masked (i.e., supported block sizes) differ for the four chip select spaces as
follows:
(multiplexed with P40-P43) are the chip select output pins for the CS0-CS3 address ranges. These
CS0 and CS1 spaces: A29-A14
CS2 and CS3 spaces: A30-A15
TMP1942-130
WAIT
CS
0
pin to insert wait states and consequently prolong read and
-
CS
3
) to assert when an address on the address bus falls
TMP1942CY/CZ