tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 132

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

BMA0
(0xFFFF_E400)
BMA1
(0xFFFF_E404)
Note: Bits 10-15 in BMA0 and BMA1 must always be set to 0.
This is because, although the CS0 and CS1 spaces can have a size of 16 KB to 1 GB, the
TMP1942’s external address space is limited to 16 MB, which requires setting bits 10-15 to 0 so as
not to mask the A24-A29 address bits.
Base/mask address registers BMA0 (0xFFFF_E400) to BMA3 (0xFFFF_E40C)
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Figure 3.7.1 Base/Mask Address Registers (BMA0 and BMA1)
15
23
31
15
23
31
7
1
0
0
0
7
1
0
0
0
Sets the size of the CS0 space. 0: Used for comparing addresses
Sets the size of the CS1 space. 0: Used for comparing addresses
14
22
30
14
22
30
6
1
0
0
0
6
1
0
0
0
TMP1942CY/CZ-131
Must always be set to 0.
Must always be set to 0.
13
21
29
13
21
29
5
1
0
0
0
5
1
0
0
0
Sets A23-A16 for the start address.
Sets A31-A24 for the start address.
Sets A23-A16 for the start address.
Sets A31-A24 for the start address.
12
20
28
12
20
28
4
1
0
0
0
4
1
0
0
0
MA0
MA0
MA1
MA1
R/W
R/W
BA0
R/W
BA0
R/W
R/W
R/W
BA1
R/W
BA1
R/W
11
19
27
11
19
27
3
1
0
0
0
3
1
0
0
0
TMP1942CY/CZ
10
18
26
10
18
26
2
1
0
0
0
2
1
0
0
0
17
25
17
25
1
1
9
1
0
0
1
1
9
1
0
0
16
24
16
24
0
1
8
1
0
0
0
1
8
1
0
0