tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 353

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

WDMOD
(0xFFFF_F090) Read/Write
WDCR
(0xFFFF_F091) Read/Write
Bit symbol
After Reset
Function
Bit symbol
After Reset
Function
Watchdog timer detection time
System Clock
<SYSCK>
Selection
SYSCR1
1 (fs)
0 (fc)
Controls
WDT
1: Enable
B1H: WDT disable code
4EH: WDT clear code
WDTE
R/W
7
7
1
Figure 3.19.5 Watchdog Timer Control Register
Figure 3.19.4 Watchdog Timer Mode Register
<GEAR1:0>
Clock Gear
Selects WDT detection
time
00: 2
01: 2
10: 2
11: 2
SYSCR1
WDTP1
01 (fc/
10 (fc/
11 (fc/
Value
00 (fc)
xxx
6
6
0
16
18
20
22
/f
/f
/f
/f
SYS
SYS
SYS
SYS
TMP1942CY/CZ-352
2
4
8
)
)
)
R/W
WDTP0
5
5
0
16.384 ms
4.096 ms
8.192 ms
2.048 ms
2.0 s
00
⎯
⎯
⎯
4
4
Watchdog Timer Detection Time
⎯
W
⎯
16.384 ms
32.768 ms
65.536 ms
Controls watchdog timer output
8.192 ms
Disables/enables watchdog timer
WDMOD<WDTP1, 0>
Other values
Disables or clears WDT
8.0 s
0
1
0
1
⎯
⎯
⎯
01
3
3
B1H
4EH
⎯
Transmit WDT output to reset
Disable
Enable
IDLE
0: Idle
1: Operate
I2WDT
TMP1942CY/CZ
2
2
0
Disable code
Clear code
⎯
131.072 ms
262.144 ms
32.768 ms
65.536 ms
@ fc = 32 MHz, fs = 32.768 kHz
32.0 s
R/W
10
1: Transmits
RESCR
WDT
output to
chip's
internal
reset pin
1
1
0
1048.576 ms
131.072 ms
262.144 ms
524.288 ms
Must
always be
set to 0.
128.0 s
R/W
11
⎯
0
0
0