tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 124

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

A [23 : 16]
AD [15 : 0]
ALE
RD
(4) Read recovery time
output of the next address can be secured even when the device is operating at a fast clock speed. Figure
3.6.10 shows a bus timing diagram where one and two dummy clock cycles are inserted.
AD [15 : 0]
ALE
AD [15 : 0]
ALE
RD
Figure 3.6.10 Read Operation Timing Diagram (with Dummy Cycles Inserted)
As shown above, by adding two dummy clock cycles, a sufficient time from the rise of
inserted to create a recovery time. Dummy cycles can only be inserted when the immediately
preceding cycle is a read cycle.
two clock cycles. Use the CS/wait controller to set the number of clock cycles.
When an external access occurs after reading from an external area, a dummy cycle can be
External read followed by external read:
External read followed by external write:
External write followed by external access: Cannot be inserted
The number of dummy cycles can be specified independently for each block as one clock cycle or
Read Data
Read Data
Dummy
DATA
Dummy cycle (1 clock cycle)
Figure 3.6.9 Read Recovery Time
TMP1942CY/CZ-123
Two clock cycles added
tsys
ADR
Can be inserted
Can be inserted
Next ADR
Upper address
tsys
Dummy cycles (2 clock cycles)
Dummy
DATA
TMP1942CY/CZ
ADR
Next ADR
RD
to the